ADG3300BRUZ Analog Devices

Low Voltage 1.15 V to 5.5 V, 8-Channel Bidirectional Logic Level Translator ADG3300 FEATURES FUNCTIONAL BLOCK DIAGRAM Bidirectional level translation V V CCA CCY Operates from 1.15 V to 5.5 V Low quiescent current <1 A A1 Y1 No direction pin A2 Y2 APPLICATIONS A3 Y3 Low voltage ASIC level translation A4 Y4 Smart card readers Cell phones and cell phone cradles A5 Y5 Portable communications devices A6 Y6 Telecommunications equipment Network switches and routers A7 Y7 Storage systems (SAN/NAS) Computing/server applications A8 Y8 GPS EN Portable POS systems GND Low cost serial interfaces Figure 1. GENERAL DESCRIPTION internally pulled down by 6 k resistors, while the Y terminals The ADG3300 is a bidirectional logic level translator that con- are in the high impedance state. The EN pin is referred to VCCA tains eight bidirectional channels. It can be used in multivoltage supply voltage and driven high for normal operation. digital system applications such as data transfer between a low voltage DSP/controller and a higher voltage device. The internal The ADG3300 is available in a compact 20-lead TSSOP package, architecture allows the device to perform bidirectional logic and it is guaranteed to operate over the 1.15 V to 5.5 V supply level translation without an additional signal to set the direction voltage range and extended 40C to +85C temperature range. of the translation. The voltage applied to VCCA sets the logic levels on the A side of the device, while VCCY sets the levels on the Y side. For proper PRODUCT HIGHLIGHTS operation, VCCA must always be less than VCCY. The VCCA-com- 1. Bidirectional level translation. patible logic signals applied to the A side of the device appear as V -compatible levels on the Y side. Similarly, V -compatible CCY CCY 2. Fully guaranteed over the 1.15 V to 5.5 V supply range. logic levels applied to the Y side of the device appear as V - CCA 3. No direction pin. compatible logic levels on the A side. 4. 20-lead TSSOP package. The enable pin provides three-state operation of the Y side pins. When the enable pin (EN) is pulled low, the A1 to A8 pins are Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 2005 Analog Devices, Inc. All rights reserved. 05061-001ADG3300 TABLE OF CONTENTS Specifications..................................................................................... 3 Input Driving Requirements..................................................... 15 Absolute Maximum Ratings............................................................ 6 Output Load Requirements ...................................................... 15 ESD Caution.................................................................................. 6 Enable Operation ....................................................................... 15 Pin Configuration and Function Descriptions............................. 7 Power Supplies............................................................................ 15 Typical Performance Characteristics ............................................. 8 Data Rate ..................................................................................... 16 Test Circuits..................................................................................... 12 Applications..................................................................................... 17 Terminology .................................................................................... 14 Layout Guidelines....................................................................... 17 Theory of Operation ...................................................................... 15 Outline Dimensions ....................................................................... 18 Level Translator Architecture.................................................... 15 Ordering Guide .......................................................................... 18 REVISION HISTORY 4/05Revision 0: Initial Version Rev. 0 Page 2 of 20