Wide Dynamic Range, High Speed, Digitally Controlled VGA Data Sheet ADL5201 FEATURES FUNCTIONAL BLOCK DIAGRAM SPI WITH FA, 11.5 dB to +20 dB gain range PARALLEL WITH LATCH, UP/DOWN INTERFACE VPOS GND PWUP 0.5 dB 0.1 dB step size 150 differential input and output 7.5 dB noise figure at maximum gain MODE0, LOGIC OIP3 > 50 dBm at 200 MHz MODE1 3 dB upper frequency bandwidth of 700 MHz Multiple control interface options VIN+ VOUT+ 0dB TO 31.5dB 150 +20dB 150 Parallel 6-bit control interface (with latch) VOUT VIN Serial peripheral interface (SPI) (with fast attack) Gain up/down mode PM Wide input dynamic range ADL5201 Low power mode option Figure 1. Power-down control Single 5 V supply operation 24-lead, 4 mm 4 mm LFCSP package APPLICATIONS Differential ADC drivers High IF sampling receivers High output power IF amplification Instrumentation GENERAL DESCRIPTION The ADL5201 is a digitally controlled, variable gain, wide band- The ADL5201 is powered on by applying the appropriate logic width amplifier that provides precise gain control, high IP3, and level to the PWUP pin. The quiescent current of the ADL5201 low noise figure. The excellent distortion performance and high is typically 80 mA in low power mode. When configured in high signal bandwidth make the ADL5201 an excellent gain control performance mode for more demanding applications, the quiescent device for a variety of receiver applications. The ADL5201 also current is 110 mA. When powered down, the ADL5201 consumes incorporates a low power mode option that lowers the supply less than 7 mA and offers excellent input-to-output isolation. current. The gain setting is preserved during power-down. For wide input dynamic range applications, the ADL5201 provides Fabricated on an Analog Devices, Inc., high speed SiGe process, a broad 31.5 dB gain range with 0.5 dB resolution. The gain is the ADL5201 provides precise gain adjustment capabilities with adjustable through multiple gain control interface options: parallel, good distortion performance and low phase error. The ADL5201 serial peripheral interface, and up/down. amplifier comes in a compact, thermally enhanced, 24-lead, 4 mm 4 mm LFCSP package and operates over the temperature Incorporating proprietary distortion cancellation techniques, range of 40C to +85C. the ADL5201 achieves an output IP3 of greater than 47 dBm at frequencies approaching 200 MHz for most gain settings. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20112015 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 09388-001ADL5201 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Logic Timing ............................................................................... 16 Applications ....................................................................................... 1 Circuit Description......................................................................... 17 Functional Block Diagram .............................................................. 1 Basic Structure ............................................................................ 17 General Description ......................................................................... 1 Input System ............................................................................... 17 Revision History ............................................................................... 2 Output Amplifier ........................................................................ 17 Specif icat ions ..................................................................................... 3 Gain Control ............................................................................... 17 Timing Diagrams .......................................................................... 4 Applications Information .............................................................. 18 Absolute Maximum Ratings ............................................................ 5 Basic Connections ...................................................................... 18 ESD Caution .................................................................................. 5 ADC Driving ............................................................................... 18 Pin Configuration and Function Descriptions ............................. 6 Layout Considerations ............................................................... 20 Typical Performance Characteristics ............................................. 7 Evaluation Board ............................................................................ 21 Characterization and Test Circuits ............................................... 14 Evaluation Board Control Software ......................................... 21 Theory of Operation ...................................................................... 15 Schematics and Artwork ........................................................... 22 Digital Interface Overview ........................................................ 15 Evaluation Board Configuration Options ............................... 24 Parallel Digital Interface ............................................................ 15 Outline Dimensions ....................................................................... 26 Serial Peripheral Interface (SPI) ............................................... 15 Ordering Guide .......................................................................... 26 Up/Down Interface .................................................................... 15 REVISION HISTORY 1/15Rev. B to Rev. C Changes to Table 1 ............................................................................ 4 Change to Table 3 ............................................................................. 6 9/13Rev. A to Rev. B Changed Logic Pins Absolute Maximum Rating from 3.6 V to 0.3 V to +3.6 V (not to exceed VPOS 0.5 V at any time) .... 5 12/12Rev. 0 to Rev. A Changes to Layout Consideration Section .................................. 20 Updated Outline Dimensions ....................................................... 26 10/11Revision 0: Initial Version Rev. C Page 2 of 26