Wide Dynamic Range, High Speed, Digitally Controlled VGA Data Sheet ADL5202 FEATURES FUNCTIONAL BLOCK DIAGRAM SIDE A Dual independent, digitally controlled VGAs SPI WITH FA, PARALLEL WITH LATCH, 11.5 dB to +20 dB gain range UP/DN PWUPA VPOS 0.5 dB 0.1 dB step size 150 differential input and output LOGIC 7.5 dB noise figure at maximum gain OIP3 > 47.5 dBm at 200 MHz VOUTA+ VINA+ 0dB TO 31.5dB 3 dB upper frequency bandwidth of 700 MHz 150 +20dB 150 VOUTA VINA Multiple control interface options MODE0, Parallel 6-bit control interface (with latch) MODE1 CONTROL CIRCUITRY Serial peripheral interface (SPI) (with fast attack) PM Gain up/down mode VINB+ VOUTB+ 0dB TO 31.5dB Wide input dynamic range 150 +20dB 150 VINB VOUTB Low power mode option Power-down control LOGIC Single 5 V supply operation ADL5202 40-lead, 6 mm 6 mm LFCSP package PWUPB GND SIDE B SPI WITH FA, APPLICATIONS PARALLEL WITH LATCH, UP/DN Differential ADC drivers Figure 1. High IF sampling receivers High output power IF amplification Instrumentation GENERAL DESCRIPTION The ADL5202 is a digitally controlled, variable gain, wide band- The ADL5202 is powered on by applying the appropriate logic width amplifier that provides precise gain control, high output level to the PWUPx pins. The quiescent current of the ADL5202 IP3, and low noise figure. The excellent distortion performance is typically 160 mA in low power mode. When configured in high and high signal bandwidth make the ADL5202 an excellent gain performance mode for more demanding applications, the quiescent control device for a variety of receiver applications. The ADL5202 current is 210 mA. When powered down, the ADL5202 consumes also incorporates a low power mode option that lowers the supply less than 14 mA and offers excellent input-to-output isolation. current. The gain setting is preserved during power-down. For wide input dynamic range applications, the ADL5202 Fabricated on an Analog Devices, Inc., high speed SiGe process, provides a broad 31.5 dB gain range with 0.5 dB resolution. The the ADL5202 provides precise gain adjustment capabilities with gain is adjustable through multiple gain control interface options: good distortion performance and low phase error. The ADL5202 parallel, serial peripheral interface, and up/down. amplifier comes in a compact, thermally enhanced 40-lead, 6 mm 6 mm LFCSP package and operates over a temperature Incorporating proprietary distortion cancellation techniques, range of 40C to +85C. the ADL5202 achieves a better than 47.5 dBm output IP3 at frequencies approaching 200 MHz for most gain settings. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. 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Technical Support www.analog.com 09387-001ADL5202 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Gain Up/Down Interface ........................................................... 16 Applications ....................................................................................... 1 Truth Table .................................................................................. 17 Functional Block Diagram .............................................................. 1 Logic Timing ............................................................................... 17 General Description ......................................................................... 1 Circuit Description......................................................................... 18 Revision History ............................................................................... 2 Basic Structure ............................................................................ 18 Specif icat ions ..................................................................................... 3 Applications Information .............................................................. 19 Absolute Maximum Ratings ............................................................ 5 Basic Connections ...................................................................... 19 ESD Caution .................................................................................. 5 ADC Driving ............................................................................... 19 Pin Configuration and Function Descriptions ............................. 6 Layout Considerations ............................................................... 21 Typical Performance Characteristics ............................................. 8 Evaluation Board ............................................................................ 22 Characterization and Test Circuits ............................................... 15 Evaluation Board Control Software ......................................... 22 Theory of Operation ...................................................................... 16 Evaluation Board Schematics and Artwork ............................ 23 Digital Interface Overview ........................................................ 16 Evaluation Board Configuration Options ............................... 27 Parallel Digital Interface ............................................................ 16 Outline Dimensions ....................................................................... 29 Serial Peripheral Interface (SPI) ............................................... 16 Ordering Guide .......................................................................... 29 REVISION HISTORY 9/2013Rev. A to Rev. B 1/2017Rev. C to Rev. D Changed Logic Pins Absolute Maximum Rating from 3.6 V to Change to Features Section and General Description Section ........ 1 0.3 V to +3.6 V (not to exceed VPOS 0.5 V at any time) .... 5 Changes to Noise/Harmonic Performance Parameter, Table 1 ....... 4 12/2012Rev. 0 to Rev. A 1/2015Rev. B to Rev. C Changes to Layout Consideration Section .................................. 21 Changes to Table 1 ............................................................................ 4 Change to Table 3 ............................................................................. 6 10/2011Revision 0: Initial Version Rev. D Page 2 of 29