100 MHz to 4000 MHz RF/IF Digitally Controlled VGA Data Sheet ADL5240 FEATURES GENERAL DESCRIPTION The ADL5240 is a high performance, digitally controlled variable Operating frequency from 100 MHz to 4000 MHz Digitally controlled VGA with serial and parallel interfaces gain amplifier (VGA) operating from 100 MHz to 4000 MHz. 6-bit, 0.5 dB digital step attenuator The VGA integrates a high performance, 20 dB gain, internally 31.5 dB gain control range with 0.25 dB step accuracy matched amplifier (AMP) with a 6-bit digital step attenuator Gain block amplifier specifications (DSA) that has a gain control range of 31.5 dB in 0.5 dB steps Gain: 19.7 dB at 2.14 GHz with 0.25 dB step accuracy. The attenuation of the DSA can be OIP3: 41.0 dBm at 2.14 GHz controlled using a serial or parallel interface. P1dB: 19.5 dBm at 2.14 GHz Both the gain block and DSA are internally matched to 50 at Noise figure: 2.9 dB at 2.14 GHz their inputs and outputs and are separately biased. The separate Gain block or digital step attenuator can be first bias allows all or part of the ADL5240 to be used, which facilitates Single supply operation from 4.75 V to 5.25 V easy reuse throughout a design. The pinout of the ADL5240 also Low quiescent current of 93 mA enables either the gain block or DSA to be first, giving the VGA Thermally efficient, 5 mm 5 mm, 32-lead LFCSP maximum flexibility in a signal chain. The companion ADL5243 integrates a W driver amplifier to The ADL5240 consumes just 93 mA and operates from a single the output of the gain block and DSA supply ranging from 4.75 V to 5.25 V. The VGA is packaged in a APPLICATIONS thermally efficient, 5 mm 5 mm, 32-lead LFCSP and is fully Wireless infrastructure specified for operation from 40C to +85C. A fully populated Automated test equipment evaluation board is available. RF/IF gain control FUNCTIONAL BLOCK DIAGRAM 32 31 30 29 28 27 26 25 1 24 VDD VDD SERIAL/PARALLEL INTERFACE NC 2 23 NC NC 3 22 NC DSAIN 4 21 DSAOUT 0.5dB 1dB 2dB 4dB 8dB 16dB NC 5 20 NC 6 19 NC NC ADL5240 AMP NC 7 18 NC NC 8 17 NC 9 10 11 12 13 14 15 16 Figure 1. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20112013 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices . Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com NC SEL AMPOUT/VCC D0/CLK NC D1/DATA NC D2/LE NC D3 NC D4 AMPIN D5 NC D6 09430-001ADL5240 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Applications Information .............................................................. 16 Applications ....................................................................................... 1 Basic Layout Connections ......................................................... 16 General Description ......................................................................... 1 SPI Timing................................................................................... 18 Functional Block Diagram .............................................................. 1 Loop Performance ...................................................................... 20 Revision History ............................................................................... 2 Amplifier Drive Level for Optimum ACLR ............................ 22 Specif icat ions ..................................................................................... 3 Thermal Considerations ............................................................ 22 Absolute Maximum Ratings ............................................................ 8 Evaluation Board ............................................................................ 23 ESD Caution .................................................................................. 8 Outline Dimensions ....................................................................... 28 Pin Configuration and Function Descriptions ............................. 9 Ordering Guide .......................................................................... 28 Typical Performance Characteristics ........................................... 10 REVISION HISTORY 6/13Rev. 0 to Rev. A Changes to Table 1 ............................................................................. 4 Changes to Table 3 ............................................................................. 9 Changes to Figure 3 ......................................................................... 11 Changes to Figure 16 ....................................................................... 12 Added Figure 29, Renumbered Sequentially ............................... 14 Changes to Table 5, Figure 35, and Figure 36 .............................. 18 Added Amplifier Drive Level for Optimum ACLR Section and Figure 39 .................................................................................... 22 Changes to Evaluation Board Section ........................................... 23 Changes to Figure 41 and Table 8 .................................................. 24 Added Figure 42 ............................................................................... 25 Changes to Figure 43 and Figure 44 .............................................. 26 Added Figure 45 ............................................................................... 27 7/11Revision 0: Initial Version Rev. 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