Cascadable IF VGAs with Programmable RMS Detectors Data Sheet ADL5336 FEATURES FUNCTIONAL BLOCK DIAGRAM COM OPP1 OPM1 IP2A IM2A COM IP2B IM2B Pair of VGAs with rms AGC detectors VGA and AGC modes of operation Continuous gain control range: 48 dB VCM1 VCM2 Noise figure = 6.8 dB at maximum gain VPOS VPOS VGA2 IMD3 >62 dBc for 1.0 V p-p composite output VGA1 INP1 OPP2 Differential input and output Multiplexed inputs for VGA2 INM1 OPM2 Programmable detector AGC setpoints VPOS 2 2 VPOS Programmable VGA maximum gain X X ADL5336 Power-down feature COM COM Single 5 V supply operation MODE SDO APPLICATIONS SPI ENBL DATA Point-to-multipoint radios Instrumentation GAIN1 DTO1 GAIN2 DTO2 COMD VPSD LE CLK Medical Figure 1. GENERAL DESCRIPTION The ADL5336 consists of a pair of variable gain amplifiers (VGAs) When driven from a 200 source or from a 50 source through designed for cascaded IF applications. The amplifiers have linear- a 1:4 balun, the noise figure (NF) for the composite amplifier is in-dB gain control and operate from low frequencies to 1 GHz. 6.8 dB at maximum gain. The output of each VGA can drive Their excellent gain conformance over the control range and 100 loads to 5 V p-p maximum. flatness over frequency are due to Analog Devices, Inc., patented Each VGA has an independent square law detector for autonomous, X-AMP architecture, an innovative technique for implementing automatic gain control (AGC) operation. Each detector setpoint high performance variable gain control. can be programmed independently through the SPI from 24 dBV Each VGA has 24 dB of gain control range. Their maximum gain to 3 dBV in 3 dB steps. When both VGAs are arranged in AGC can be independently programmable over a 6 dB range via the mode and are programmed to the same setpoint, the composite NF increases to 9 dB when backed off by 18 dB from maximum gain. SPI. The VGAs can be cascaded to provide a total range of 48 dB. When connected to a 50 source through a 1:4 balun, the gain The ADL5336 operates from a 5 V supply and consumes a typical is 6 dB higher. The second VGA has an SPI programmable input supply current of 80 mA. When disabled, it consumes 4 mA. It is switch that selects one of two external inputs. fabricated in an advanced silicon-germanium BiCMOS process and is available in a 32-lead exposed paddle LFCSP package. Performance is specified over a 40C to +85C temperature range. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20112018 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 09550-001ADL5336 Data Sheet TABLE OF CONTENTS Basic Connections ...................................................................... 20 Features .............................................................................................. 1 Supply Decoupling ..................................................................... 20 Applications ....................................................................................... 1 Input Signal Path ........................................................................ 20 Functional Block Diagram .............................................................. 1 Output Signal Path ..................................................................... 20 General Description ......................................................................... 1 Detector Output and Gain Pin ................................................. 21 Revision History ............................................................................... 2 Common-Mode Bypassing ....................................................... 21 Specifications ..................................................................................... 3 Serial Port Connections ............................................................. 21 Timing Diagrams .......................................................................... 5 Mode and Enable Connections ................................................ 21 Absolute Maximum Ratings ............................................................ 6 Error Vector Magnitude (EVM) ............................................... 21 ESD Caution .................................................................................. 6 Effect of CAGC on EVM ............................................................... 22 Pin Configuration and Function Descriptions ............................. 7 AGC Insensitivity to Modulation Type ................................... 22 Typical Performance Characteristics ............................................. 8 Effect of Setpoint on EVM ........................................................ 23 Theory of Operation ...................................................................... 17 Cascaded VGA/AGC Performance .......................................... 23 Circuit Description..................................................................... 17 Evaluation Board Layout ............................................................... 25 Gain Control Interface ............................................................... 18 Bill of Materials (BOM) ............................................................. 28 Input and Output Impedances .................................................. 18 Evaluation Board Control Software ......................................... 29 AGC Operation ........................................................................... 18 Outline Dimensions ....................................................................... 30 Register Map and Codes ................................................................ 19 Ordering Guide .......................................................................... 30 Applications Information .............................................................. 20 REVISION HISTORY 4/2018Rev. B to Rev. C Changes to Figure 4 .......................................................................... 7 6/2011Rev. 0 to Rev. A Updated Outline Dimensions ....................................................... 30 Changes to Table 1 ............................................................................. 3 Changes to Ordering Guide .......................................................... 30 Changes to Typical Performance Charteristics Section Format ...................................................................................8 2/2012Rev. A to Rev. B Changes to Figure 7 and Figure 10 .................................................. 8 Changes to Figure 70 ...................................................................... 25 Changes to Figure 11 to Figure 16 ................................................... 9 Changes to Figure 17 to Figure 22 ................................................ 10 Changes to Figure 71 and Figure 72 ............................................. 26 Changes to Table 11 ........................................................................ 28 Changes to Figure 23 and Figure 26............................................. 11 Changes to Figure 73 ...................................................................... 29 Inserted Figure 53 and Figure 56 Renumbered Sequentially .. 16 Updated Outline Dimensions ....................................................... 30 Changes to Figure 60 ...................................................................... 17 Changes to Figure 61 Caption ...................................................... 18 Changes to Cascaded VGA/AGC Performance Section and Figure 68 .......................................................................................... 24 Changes to Figure 72 ...................................................................... 26 2/2011Revision 0: Initial Version Rev. C Page 2 of 30