1200 MHz to 2500 MHz Balanced Mixer, LO Buffer, IF Amplifier, and RF Balun Data Sheet ADL5355 FEATURES FUNCTIONAL BLOCK DIAGRAM IFGM IFOP IFON PWDN LEXT RF frequency range of 1200 MHz to 2500 MHz 20 19 18 17 16 IF frequency range of 30 MHz to 450 MHz Power conversion gain: 8.4 dB ADL5355 VPIF 1 15 LOI2 SSB noise figure of 9.2 dB SSB noise figure with 5 dBm blocker of 20 dB Input IP3 of 27 dBm RFIN 2 14 VPSW Input P1dB of 10.4 dBm Typical LO drive of 0 dBm Single-ended, 50 RF and LO input ports 3 13 RFCT VGS1 High isolation SPDT LO input switch Single-supply operation: 3.3 V to 5 V BIAS GENERATOR Exposed paddle 5 mm 5 mm, 20-lead LFCSP COMM 4 12 VGS0 1500 V HBM/500 V FICDM ESD performance APPLICATIONS COMM 5 11 LOI1 Cellular base station receivers 6 7 8 9 10 Transmit observation receivers VLO3 LGM3 VLO2 LOSW NC Radio link downconverters NC = NO CONNECT Figure 1. GENERAL DESCRIPTION The ADL5355 provides two switched LO paths that can be The ADL5355 uses a highly linear, doubly balanced passive used in TDD applications where it is desirable to rapidly switch mixer core along with integrated RF and LO balancing circuitry between two local oscillators. LO current can be externally set to allow for single-ended operation. The ADL5355 incorporates using a resistor to minimize dc current commensurate with the an RF balun, allowing for optimal performance over a 1200 MHz desired level of performance. For low voltage applications, the to 2500 MHz RF input frequency range using low-side LO ADL5355 is capable of operation at voltages down to 3.3 V with injection for RF frequencies from 1700 MHz to 2500 MHz and substantially reduced current. Under low voltage operation, an high-side LO injection for RF frequencies from 1200 MHz to additional logic pin is provided to power down (<200 A) the 1700 MHz. The balanced passive mixer arrangement provides circuit when desired. good LO-to-RF leakage, typically better than 39 dBm, and The ADL5355 is fabricated using a BiCMOS high performance excellent intermodulation performance. The balanced mixer IC process. The device is available in a 5 mm 5 mm, 20-lead core also provides extremely high input linearity, allowing the LFCSP and operates over a 40C to +85C temperature range. device to be used in demanding cellular applications where in- An evaluation board is also available. band blocking signals may otherwise result in the degradation of dynamic performance. A high linearity IF buffer amplifier Table 1. Passive Mixers follows the passive mixer core to yield a typical power conversion Single Single Mixer Dual Mixer RF Frequency (MHz) Mixer and IF Amp and IF Amp gain of 8.4 dB and can be used with a wide range of output impedances. 500 to 1700 ADL5367 ADL5357 ADL5358 1200 to 2500 ADL5365 ADL5355 ADL5356 2300 to 2900 ADL5363 ADL5353 ADL5354 Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20092015 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 08080-001ADL5355 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 5 V Performance ............................................................................8 Applications ....................................................................................... 1 3.3 V Performance ...................................................................... 15 General Description ......................................................................... 1 Circuit Description......................................................................... 16 Functional Block Diagram .............................................................. 1 RF Subsystem .............................................................................. 16 Revision History ............................................................................... 2 LO Subsystem ............................................................................. 17 Specifications ..................................................................................... 3 Applications Information .............................................................. 18 5 V Performance ........................................................................... 4 Basic Connections ...................................................................... 18 3.3 V Performance ........................................................................ 4 IF Port .......................................................................................... 18 Spur Tables .................................................................................... 5 Bias Resistor Selection ............................................................... 18 Absolute Maximum Ratings ............................................................ 6 Mixer VGS Control DAC .......................................................... 18 ESD Caution .................................................................................. 6 Evaluation Board ............................................................................ 20 Pin Configuration and Function Descriptions ............................. 7 Outline Dimensions ....................................................................... 23 Typical Performance Characteristics ............................................. 8 Ordering Guide .......................................................................... 23 REVISION HISTORY 2/15Rev. 0 to Rev. A Added Table 1 Renumbered Sequentially .................................... 1 Changes to Figure 2 .......................................................................... 7 Deleted R9 = 1.1 k, 5 V Performance Section ........................... 8 Deleted Figure 41 Renumbered Sequentially............................. 14 Changes to Figure 42 ...................................................................... 14 Changes to Figure 52 ...................................................................... 20 Changed R9 = 1.1 k to R9 = 1.7 k, Table 9 ............................ 21 Updated Outline Dimensions ....................................................... 23 Changes to Ordering Guide .......................................................... 23 7/09Revision 0: Initial Version Rev. A Page 2 of 23