500 MHz to 1700 MHz Balanced Mixer, LO Buffer and RF Balun Data Sheet ADL5367 FEATURES FUNCTIONAL BLOCK DIAGRAM VCMI IFOP IFON PWDN COMM RF frequency range of 500 MHz to 1700 MHz 20 19 18 17 16 IF frequency range of 30 MHz to 450 MHz Power conversion loss: 7.7 dB ADL5367 1 15 VPMX LOI2 SSB noise figure of 8.3 dB SSB noise figure with 5 dBm blocker of 21 dB Input IP3 of 34 dBm 2 14 RFIN VPSW Typical LO drive of 0 dBm Single-ended, 50 RF and LO input ports High isolation SPDT LO input switch RFCT 3 13 VGS1 Single-supply operation: 3.3 V to 5 V BIAS Exposed paddle 5 mm 5 mm, 20-lead LFCSP GENERATOR 1500 V HBM/500 V FICDM ESD performance COMM 4 12 VGS0 APPLICATIONS Cellular base station receivers COMM 5 11 LOI1 Transmit observation receivers 6 7 8 9 10 Radio link downconverters VLO3 LGM3 VLO2 LOSW NC GENERAL DESCRIPTION NC = NO CONNECT The ADL5367 uses a highly linear, doubly balanced passive Figure 1. mixer core along with integrated RF and LO balancing circuitry The ADL5367 provides two switched LO paths that can be to allow for single-ended operation. The ADL5367 incorporates used in TDD applications where it is desirable to rapidly switch an RF balun, allowing optimal performance over a 500 MHz to between two local oscillators. LO current can be externally set 1700 MHz RF input frequency range. Performance is optimized for using a resistor to minimize dc current commensurate with the RF frequencies from 500 MHz to 1200 MHz using a high-side LO desired level of performance. For low voltage applications, the and for RF frequencies from 900 MHz to 1700 MHz using a ADL5367 is capable of operation at voltages down to 3.3 V with low-side LO. The balanced passive mixer arrangement provides substantially reduced current. Under low voltage operation, an good LO to RF leakage, typically better than 35 dBm, and additional logic pin is provided to power down (<200 A) the excellent intermodulation performance. The balanced mixer circuit when desired. core also provides extremely high input linearity, allowing the The ADL5367 is fabricated using a BiCMOS high performance device to be used in demanding cellular applications where in- IC process. The device is available in a 5 mm 5 mm, 20-lead band blocking signals may otherwise result in the degradation LFCSP and operates over a 40C to +85C temperature range. of dynamic performance. A high linearity IF buffer amplifier An evaluation board is also available. follows the passive mixer core to yield a typical power conversion loss of 7.7 dB and can be used with a wide range of output Table 1. Passive Mixers impedances. Single Single Mixer Dual Mixer RF Frequency (MHz) Mixer and IF Amp and IF Amp 500 to 1700 ADL5367 ADL5357 ADL5358 1200 to 2500 ADL5365 ADL5355 ADL5356 2300 to 2900 ADL5363 ADL5353 ADL5354 Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20092016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 08083-001ADL5367 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Upconversion .............................................................................. 15 Applications ....................................................................................... 1 Spur Tables .................................................................................. 16 General Description ......................................................................... 1 Circuit Description......................................................................... 17 Functional Block Diagram .............................................................. 1 RF Subsystem .............................................................................. 17 Revision History ............................................................................... 2 LO Subsystem ............................................................................. 17 Specifications ..................................................................................... 3 Applications Information .............................................................. 19 5 V Performance ........................................................................... 4 Basic Connections ...................................................................... 19 3.3 V Performance ........................................................................ 4 IF Port .......................................................................................... 19 Absolute Maximum Ratings ............................................................ 5 Mixer VGS Control DAC .......................................................... 19 ESD Caution .................................................................................. 5 Evaluation Board ............................................................................ 20 Pin Configuration and Function Descriptions ............................. 6 Outline Dimensions ....................................................................... 23 Typical Performance Characteristics ............................................. 7 Ordering Guide .......................................................................... 23 5 V Performance ........................................................................... 7 3.3 V Performance ...................................................................... 14 REVISION HISTORY 3/16Rev. B to Rev. C Added Thermal Resistance Section and Junction to Board Thermal Impedance Section ............................................... 5 Changes to Figure 2 .......................................................................... 6 Change to Evaluation Board Section and Figure 49 .................. 20 2/15Rev. A to Rev. B Changes to Table 1 ............................................................................ 1 Deleted Figure 37 and Figure 39 ................................................... 13 Deleted Bias Resistor Selection Section ....................................... 19 Changes to Figure 49 ...................................................................... 20 Changes to Table 7 .......................................................................... 21 Updated Outline Dimensions ....................................................... 23 Changes to Ordering Guide .......................................................... 23 10/09Revision 0: Initial Version Rev. B Page 2 of 24