RF/IF Vector Multiplier Data Sheet ADL5390 FEATURES FUNCTIONAL BLOCK DIAGRAM VPRF QBBP OBBM VPS2 Matched pair of multiplying VGAs Broad frequency range 20 MHz to 2.4 GHz INMQ Continuous magnitude control from +5 dB to 30 dB INPQ Output third-order intercept 24 dBm RFOP CMRF Output 1 dB compression point 11 dBm RFOM INPI Output noise floor 148 dBm/Hz INMI Adjustable modulation bandwidth up to 230 MHz Fast output power disable CMOP IBBP IBBM DSOP Single-supply voltage 4.75 V to 5.25 V APPLICATIONS Figure 1. PA linearization and predistortion Amplitude and phase modulation Variable matched attenuator and/or phase shifter Cellular base stations Radio links Fixed wireless access Broadband/CATV RF/IF analog multiplexer The gain control inputs are dc-coupled with a 500 mV differential GENERAL DESCRIPTION full-scale range centered about a 500 mV common mode. The The ADL5390 vector multiplier consists of a matched pair of maximum modulation bandwidth is 230 MHz, which can be broadband variable gain amplifiers whose outputs are summed. reduced by adding external capacitors to limit the noise bandwidth The separate gain controls for each amplifier are linear-in- on the control lines. magnitude. If the two input RF signals are in quadrature, the Both the RF inputs and outputs can be used differentially or vector multiplier can be configured as a vector modulator or as single-ended and must be ac-coupled. The impedance of each a variable attenuator/phase shifter by using the gain control pins VGA RF input is 250 to ground, and the differential output as Cartesian variables. In this case, the output amplitude can be controlled from a maximum of +5 dB to less than 30 dB, and impedance is nominally 50 over the operating frequency the phase can be shifted continuously over the entire 360 range. range. The DSOP pin allows the output stage to be disabled Since the signal paths are linear, the original modulation on the quickly to protect subsequent stages from overdrive. The ADL5390 operates off supply voltages from 4.75 V to 5.25 V inputs is preserved. If the two signals are independent, then the while consuming 135 mA. vector multiplier can function as a 2:1 multiplexer or can provide fading from one channel to another. The ADL5390 is fabricated on Analog Devices proprietary, high performance 25 GHz SOI complementary bipolar IC The ADL5390 operates over a wide frequency range of 20 MHz process. It is available in a 24-lead, Pb-free CSP package and to 2400 MHz. For a maximum gain setting on one channel at 380 MHz, the ADL5390 delivers an OP1dB of 11 dBm, an OIP3 operates over a 40C to +85C temperature range. Evaluation of 24 dBm, and an output noise floor of 148 dBm/Hz. The gain boards are available. and phase matching between the two VGAs is better than 0.5 dB and 1, respectively, over most of the operating range. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20042017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 04954-001ADL5390 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Using the ADL5390 .................................................................... 12 Applications ....................................................................................... 1 RF Input and Matching ............................................................. 12 Functional Block Diagram .............................................................. 1 RF Output and Matching .......................................................... 13 General Description ......................................................................... 1 Driving the I-Q Baseband Gain Controls ............................... 13 Specifications ..................................................................................... 3 Interfacing to High Speed DACs .............................................. 14 Absolute Maximum Ratings ............................................................ 5 Generalized Modulator ............................................................. 15 ESD Caution .................................................................................. 5 Vector Modulator ....................................................................... 15 Pin Configuration and Function Descriptions ............................. 6 Vector Modulator ExampleCDMA2000 ............................. 15 Typical Performance Characteristics ............................................. 7 Quadrature Modulator .............................................................. 17 General Structure ........................................................................... 11 RF Multiplexer ............................................................................ 18 Theory of Operation .................................................................. 11 Evaluation Board ............................................................................ 19 Noise and Distortion .................................................................. 11 Outline Dimensions ....................................................................... 23 Applications Information .............................................................. 12 Ordering Guide .......................................................................... 23 REVISION HISTORY 10/2017Rev. 0 to Rev. A Changed CP-24-2 to CP-24-10 .................................... Throughout Updated Outline Dimensions ....................................................... 23 Changes to Ordering Guide .......................................................... 23 10/2004Revision 0: Initial Version Rev. A Page 2 of 23