50 MHz to 6 GHz TruPwr Detector ADL5501 5 FEATURES True rms response Excellent temperature stability Up to 30 dB input dynamic range 1 50 input impedance 1.25 V rms, 15 dBm, maximum input Single-supply operation: 2.7 V to 5.5 V Low power: 3.3 mW at 3 V supply RoHS-compliant 0.1 APPLICATIONS 0.03 Measurement of CDMA-, CDMA2000-, W-CDMA-, and QPSK-/ 25 20 15 10 5 0 5 10 15 QAM-based OFDM, and other complex modulation INPUT (dBm) waveforms Figure 1. Output vs. Input Level, Supply = 3 V, Frequency = 1.9 GHz RF transmitter or receiver power measurement GENERAL DESCRIPTION The ADL5501 is a mean-responding TruPwr power detector The on-chip, 100 series resistance at the output, combined for use in high frequency receiver and transmitter signal chains with an external shunt capacitor, creates a low-pass filter response from 50 MHz to 6 GHz. It is easy to apply, requiring only a single that reduces the residual ripple in the dc output voltage. For more supply between 2.7 V and 5.5 V and a power supply decoupling complex waveforms, an external capacitor at the FLTR pin can capacitor. The input is internally ac-coupled and has a nominal be used for supplementary signal demodulation. input impedance of 50 . The output is a linear-responding dc The ADL5501 offers excellent temperature stability across a voltage with a conversion gain of 6.3 V/V rms at 900 MHz. 30 dB range and near 0 dB measurement error across temperature The ADL5501 is intended for true power measurement of simple over the top portion of the dynamic range. In addition to its and complex waveforms. The device is particularly useful for temperature stability, the ADL5501 offers low process variations measuring high crest factor (high peak-to-rms ratio) signals, that further reduce calibration complexity. such as CDMA-, CDMA2000-, W-CDMA-, and QPSK-/QAM- The ADL5501 operates from 40C to +85C and is available in based OFDM waveforms. The on-chip modulation filter provides a small 6-lead SC-70 package. It is fabricated on a proprietary adequate averaging for most waveforms. high f silicon bipolar process. T FUNCTIONAL BLOCK DIAGRAM VPOS ADL5501 INTERNAL FILTER i CAPACITOR 2 x FLTR RFIN TRANS- CONDICTANCE ERROR CELLS AMP i 2 x BUFFER VRMS 100 BAND-GAP ENBL REFERENCE COMM Figure 2. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 20062009 Analog Devices, Inc. All rights reserved. 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OUTPUT (V) 06056-002 06056-001ADL5501 TABLE OF CONTENTS Features .............................................................................................. 1 Input Coupling Using a Series Resistor ................................... 19 Applications ....................................................................................... 1 Multiple RF Inputs ..................................................................... 19 General Description ......................................................................... 1 Selecting the Square-Domain Filter and Output Low-Pass Filter ............................................................................................. 19 Functional Block Diagram .............................................................. 1 Power Consumption, Enable, and Power-On/Power-Off Revision History ............................................................................... 2 Response Time ............................................................................ 20 Specif icat ions ..................................................................................... 3 Output Drive Capability and Buffering ................................... 21 Absolute Maximum Ratings ............................................................ 9 VRMS Output Offset ................................................................. 21 ESD Caution .................................................................................. 9 Device Calibration and Error Calculation .............................. 22 Pin Configuration and Function Descriptions ........................... 10 Calibration for Improved Accuracy ......................................... 22 Typical Performance Characteristics ........................................... 11 Drift over a Reduced Temperature Range .............................. 23 Circuit Description ......................................................................... 17 Operation Below 100 MHz ....................................................... 23 Filtering ........................................................................................ 17 Evaluation Board ........................................................................ 23 Applications Information .............................................................. 18 Outline Dimensions ....................................................................... 25 Basic Connections ...................................................................... 18 Ordering Guide .......................................................................... 25 Output Swing .............................................................................. 18 Linearity ....................................................................................... 18 REVISION HISTORY 3/09Rev. A to Rev. B 10/07Rev. 0 to Rev. A Change to Features ........................................................................... 1 Changes to General Description ..................................................... 1 Changes to Table 1 ............................................................................ 3 Changes to Table 1 ............................................................................. 3 Changes to Figure 4, Figure 5, Figure 7, and Figure 9 ............... 10 Changes to Figure 30, Figure 32, and Figure 33 ......................... 14 Deleted Figure 17 and Figure 21 Renumbered Sequentially ... 12 Changes to Figure 35, Figure 37, and Figure 38 ......................... 15 Changes to Figure 18 and Figure 21 ............................................. 13 Changes to Circuit Description Section ...................................... 16 Changes to Figure 36 and Figure 39 ............................................. 16 Changes to Layout and Operation Below 100 MHz and Changes to Figure 42 ...................................................................... 18 Above 4.0 GHz Section .................................................................. 22 Changes to Operation Below 100 MHz Section ......................... 23 Inserted Figure 56 ........................................................................... 22 Deleted Figure 56 ............................................................................ 22 Inserted Figure 57 ........................................................................... 23 Deleted Figure 57 ............................................................................ 23 Changes to Figure 58 ...................................................................... 23 Deleted Figure 57 and Figure 58 .................................................. 24 Changes to Figure 59 and Figure 60............................................. 24 9/06Revision 0: Initial Version Rev. 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