450 MHz to 6000 MHz Crest Factor Detector ADL5502 FEATURES FUNCTIONAL BLOCK DIAGRAM VPOS True rms response detector INTERNAL Envelope peak hold output ADL5502 FILTERING 4nF 1k Excellent temperature stability FLTR 0.25 dB rms detection accuracy vs. temperature 100 RMS CORE VRMS 0.25 dB envelope detection accuracy vs. temperature over the top 25 dB of the input range RFIN BUFFERS 100 Over 35 dB input power dynamic range, inclusive of crest factor PEAK/ PEAK ENVELOPE RF bandwidths from 450 MHz to 6 GHz ENBL Envelope bandwidths of 10 MHz CNTL 500 input impedance COMM Single-supply operation: 2.5 V to 3.3 V Figure 1. Low power: 3 mA at 3 V supply RoHS-compliant part PEAK RF INPUT VRMS APPLICATIONS Power and envelope measurement of W-CDMA, CDMA2000, and QPSK-/QAM-based OFDM, and other complex modulation waveforms RF transmitter or receiver power and envelope measurement CNTL ENV TRACK PEAK HOLD 1s/DIV Figure 2. GENERAL DESCRIPTION The ADL5502 is a mean-responding (true rms) power detector The ADL5502 is a highly accurate, easy to use means of in combination with an envelope detector to accurately determine determining the rms and peak to the average value of complex the crest factor of a modulated signal. It can be used in high waveforms. It can be used for crest factor measurements of both frequency receiver and transmitter signal chains from 450 MHz simple and complex waveforms but is particularly useful for to 6 GHz with envelope bandwidths over 10 MHz. Requiring measuring high crest factor (high peak-to-rms ratio) signals, only a single supply between 2.5 V and 3.3 V, the detector draws such as W-CDMA, CDMA2000, and QPSK-/QAM-based less than 3 mA. The input is internally ac-coupled and has a OFDM waveforms. The peak hold function allows the capture nominal input impedance of 500 . of short peaks in the envelope with lower sampling rate ADCs. The rms output is a linear-responding dc voltage with a conversion The crest factor detector operates from 40C to +85C and is gain of 1.8 V/V rms at 900 MHz. The peak envelope output with a available in an 8-ball, 1.5 mm 1.5 mm wafer-level chip scale conversion gain of 1.2 V/V is toggled for peak hold with less package. It is fabricated on a high f silicon BiCMOS process. T than 1% output voltage droop in over 1 ms. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 20082011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 07631-002 07631-001ADL5502 TABLE OF CONTENTS Features .............................................................................................. 1 RF Input Interfacing ................................................................... 16 Applications ....................................................................................... 1 Linearity ....................................................................................... 17 Functional Block Diagram .............................................................. 1 Output Drive Capability and Buffering ................................... 18 General Description ......................................................................... 1 Selecting the Square-Domain Filter and Output Low-Pass Filter ............................................................................................. 18 Revision History ............................................................................... 2 Power Consumption, Enable, and Power-On/Power-Off Specif icat ions ..................................................................................... 3 Response Time ............................................................................ 19 Absolute Maximum Ratings ............................................................ 6 Device Calibration and Error Calculation .............................. 19 ESD Caution .................................................................................. 6 Calibration for Improved Accuracy ......................................... 20 Pin Configuration and Function Descriptions ............................. 7 Calculation of Crest Factor (CF) .............................................. 20 Typical Performance Characteristics ............................................. 8 Drift over a Reduced Temperature Range .............................. 21 Circuit Description ......................................................................... 15 Operation at High Frequencies ................................................ 22 RMS Circuit Description and Filtering ................................... 15 Device Handling ......................................................................... 22 Filtering ........................................................................................ 15 Evaluation Board ........................................................................ 23 Envelope Peak-Hold Circuit ..................................................... 15 Outline Dimensions ....................................................................... 25 Output Buffers ............................................................................ 15 Ordering Guide .......................................................................... 25 Measuring the Crest Factor ....................................................... 15 Applications Information .............................................................. 16 Basic Connections ...................................................................... 16 REVISION HISTORY 1/11Rev. 0 to Rev. A Changes to Output Intercept Parameters, Table 1 ........................ 3 Changes to Figure 34 ...................................................................... 13 10/08Revision 0: Initial Version Rev. A Page 2 of 28