400 MHz to 4000 MHz Low Noise Amplifier Data Sheet ADL5521 FEATURES FUNCTIONAL BLOCK DIAGRAM Operation from 400 MHz to 4000 MHz ACTIVE VBIAS 1 8VPOS BIAS Noise figure of 0.8 dB at 900 MHz 7RFOUT RFIN 2 Requires few external components Integrated active bias control circuit NIC 3 6NIC Integrated dc blocking capacitors NIC 4 5NIC Adjustable bias for low power applications ADL5521 Single-supply operation from 3 V to 5 V NIC = NO INTERNAL CONNECTION. DO NOT CONNECT TO THIS PIN. Gain of 20.8 dB at 900 MHz Figure 1. OIP3 of 37.0 dBm at 900 MHz P1dB of 21.8 dBm at 900 MHz Small footprint LFCSP Pin-compatible version with 21.5 dB gain available GENERAL DESCRIPTION The ADL5521 is a high performance GaAs pHEMT low noise The ADL5521 is easy to tune, requiring only a few external amplifier. It provides high gain and low noise figure for single- components. The device can support operation from 3 V to 5 V, downconversion IF sampling receiver architectures as well as and the current draw can be adjusted with the external bias direct-downconversion receivers. resistor for applications requiring low power consumption. The ADL5521 provides a high level of integration by incorporating The ADL5521 comes in a compact, thermally enhanced, 3 mm the active bias and dc blocking capacitors, making it very easy 3 mm LFCSP and operates over the temperature range of to use while not sacrificing design flexibility. 40C to +85 C. A fully populated evaluation board is also available. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20082017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 06828-001ADL5521 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 900 MHz, VPOS = 3 V .............................................................. 11 Functional Block Diagram .............................................................. 1 1950 MHz, VPOS = 3 V ............................................................ 12 General Description ......................................................................... 1 2600 MHz, VPOS = 3 V ............................................................ 13 Revision History ............................................................................... 2 3500 MHz, VPOS = 3 V ............................................................ 14 Specifications ..................................................................................... 3 DC Characteristics ..................................................................... 15 AC Specifications .......................................................................... 3 Basic Connections .......................................................................... 16 DC Specifications ......................................................................... 4 Evaluation Board ............................................................................ 17 De-Embedded S-Parameters, VPOS = 3 V to 5 V, RFIN = Soldering Information and Recommended PCB Land Port 1, VPOS = Port 2, RFOUT = Port 3 .................................. 4 Pattern .......................................................................................... 17 Absolute Maximum Ratings ............................................................ 5 Tuning the ADL5521 for Optimal Noise Figure ........................ 18 ESD Caution .................................................................................. 5 Tuning S22 ................................................................................... 18 Pin Configuration and Function Descriptions ............................. 6 Tuning the LNA Input for Optimal Gain ................................ 19 Typical Performance Characteristics ............................................. 7 Tuning the LNA Input for Optimal Noise Figure .................. 19 900 MHz, VPOS = 5 V ................................................................. 7 S11 of the LNA with S22 Matched ........................................... 20 1950 MHz, VPOS = 5 V .............................................................. 8 Outline Dimensions ....................................................................... 21 2600 MHz, VPOS = 5 V .............................................................. 9 Ordering Guide .......................................................................... 21 3500 MHz, VPOS = 5 V ............................................................ 10 REVISION HISTORY 8/2017Rev. B to Rev. C Changed CP-8-2 to CP-8-13 ........................................ Throughout Updated Outline Dimensions ....................................................... 21 Changes to Ordering Guide .......................................................... 21 11/2013Rev. A to Rev. B Added Figure 52, Renumbered Sequentially .............................. 15 9/2009Rev. 0 to Rev. A Updated Maximum Junction Temperature Unit (Table 4) ......... 5 10/2008Revision 0: Initial Version Rev. C Page 2 of 24