2.9 GHz Ultralow Distortion RF/IF Differential Amplifier Data Sheet ADL5561 FEATURES FUNCTIONAL BLOCK DIAGRAM VCC 3 dB bandwidth of 2.9 GHz (A = 6 dB) V R Low supply current: 40 mA F Pin-strappable gain adjust: 6 dB, 12 dB, 15.5 dB ENBL Differential or single-ended input to differential output R G2 VON VIP2 Low noise input stage: 2.1 nV/Hz RTI at A = 12 dB V R G1 Low broadband distortion (A = 6 dB) V VIP1 VCOM 10 MHz: 94 dBc HD2, 87 dBc HD3 R G1 VIN1 70 MHz: 98 dBc HD2, 87 dBc HD3 R G2 140 MHz: 95 dBc HD2, 87 dBc HD3 VOP VIN2 250 MHz: 80 dBc HD2, 73 dBc HD3 GND IMD3s of 86 dBc at 250 MHz center R F ADL5561 Slew rate: 9.8 V/ns GND Fast settling of 2 ns and overdrive recovery of 3 ns Single-supply operation: 3 V to 3.6 V Figure 1. Power-down control Fabricated using the high speed XFCB3 SiGe process APPLICATIONS Differential ADC drivers Single-ended-to-differential conversion RF/IF gain blocks SAW filter interfacing GENERAL DESCRIPTION The ADL5561 is a high performance differential amplifier The device is optimized for wideband, low distortion performance. optimized for RF and IF applications. The amplifier offers low These attributes, together with its adjustable gain capability, noise of 2.1 nV/Hz and excellent distortion performance over make this device the amplifier of choice for general-purpose IF a wide frequency range, making it an ideal driver for high speed and broadband applications where low distortion, noise, and power 8-bit to 16-bit analog-to-digital converters (ADCs). are critical. This device is optimized for the best combination of slew speed, bandwidth, and broadband distortion. These attributes The ADL5561 provides three gain levels of 6 dB, 12 dB, and 15.5 dB allow it to drive a wide variety of ADCs and make it ideally suited through a pin-strappable configuration. For the single-ended for driving mixers, pin diode attenuators, SAW filters, and multi- input configuration, the gains are reduced to 5.6 dB, 11.1 dB, and element discrete devices. 14.1 dB. Using an external series input resistor expands the amplifier gain flexibility and allows for any gain selection from Fabricated on the Analog Devices, Inc., high speed SiGe process, 0 dB to 15.5 dB. the ADL5561 is supplied in a compact 3 mm 3 mm, 16-lead LFCSP package and operates over the temperature range of The quiescent current of the ADL5561 is typically 40 mA and, 40C to +85C. when disabled, consumes less than 3 mA, offering excellent input-to-output isolation. Rev. G Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20092017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 08004-001ADL5561 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Applications Information .............................................................. 14 Applications ....................................................................................... 1 Basic Connections ...................................................................... 14 Functional Block Diagram .............................................................. 1 Input and Output Interfacing ................................................... 15 General Description ......................................................................... 1 Gain Adjustment and Interfacing ............................................ 16 Revision History ............................................................................... 2 ADC Interfacing ......................................................................... 16 Specifications ..................................................................................... 3 Layout Considerations ............................................................... 18 Absolute Maximum Ratings ............................................................ 6 Soldering Information ............................................................... 19 ESD Caution .................................................................................. 6 Evaluation Board ........................................................................ 19 Pin Configuration and Function Descriptions ............................. 7 Outline Dimensions ....................................................................... 21 Typical Performance Characteristics ............................................. 8 Ordering Guide .......................................................................... 21 Circuit Description ......................................................................... 13 Basic Structure ............................................................................ 13 REVISION HISTORY 9/2017Rev. F to Rev. G 3/2010Rev A to Rev. B Changed CP-16-2 to CP-16-27 .................................... Throughout Changes to Figure 43 ...................................................................... 21 Updated Outline Dimensions ....................................................... 21 Changes to Ordering Guide .......................................................... 21 Changes to Ordering Guide .......................................................... 21 9/2009Rev 0 to Rev. A 1/2014Rev. E to Rev. F Changes to Features Section ............................................................ 1 Changes to ENBL Threshold Parameter, Table 1 ......................... 3 Changes to Table 1 ............................................................................. 3 Changes to Figure 5 ........................................................................... 8 9/2013Rev. D to Rev. E Changes to Figure 9 and Figure 10 .................................................. 9 Added Input Resistance Tolerance of 10% ................................. 3 Changes to Equation 1, Figure 32, and Figure 34 ...................... 15 Changes to Equation 2 ................................................................... 16 4/2013Rev. C to Rev. D Changes to Figure 38, Figure 39, Figure 40, and Table 9........... 17 Changes to Table 1 ............................................................................ 3 Changes to Figure 43 ...................................................................... 19 Changes to Figure 6 and Figure 7 ................................................... 8 Moved Table 14 to ......................................................................... 19 6/2011Rev. B to Rev. C 5/2009Revision 0: Initial Version Changes to Figure 28 and Figure 29 ............................................. 12 Added Figure 30 and Figure 31 Renumbered Sequentially ..... 12 Changes to Ordering Guide .......................................................... 21 Rev. G Page 2 of 24