3.3 GHz Ultralow Distortion RF/IF Differential Amplifier Data Sheet ADL5562 FEATURES FUNCTIONAL BLOCK DIAGRAM VCC 3 dB bandwidth of 3.3 GHz (A = 6 dB) V Pin-strappable gain adjust: 6 dB, 12 dB, 15.5 dB R F Differential or single-ended input to differential output ENBL Low noise input stage: 2.1 nV/Hz RTI at A = 12 dB V R G2 VON Low broadband distortion (A = 6 dB) VIP2 V 10 MHz: 91 dBc HD2, 98 dBc HD3 R G1 VIP1 VCOM 70 MHz: 102 dBc HD2, 90 dBc HD3 R G1 VIN1 140 MHz: 104 dBc HD2, 87 dBc HD3 R 250 MHz: 80 dBc HD2, 94 dBc HD3 G2 VOP VIN2 IMD3s of 94 dBc at 250 MHz center Slew rate: 9.8 V/ns R F Fast settling of 2 ns and overdrive recovery of 3 ns ADL5562 Single-supply operation: 3 V to 3.6 V GND Power-down control Figure 1. Fabricated using the high speed XFCB3 SiGe process APPLICATIONS Differential ADC drivers Single-ended to differential conversion RF/IF gain blocks SAW filter interfacing GENERAL DESCRIPTION The ADL5562 is a high performance differential amplifier The device is optimized for wideband, low distortion optimized for RF and IF applications. The amplifier offers low performance. These attributes, together with its adjustable gain noise of 2.1 nV/Hz and excellent distortion performance over capability, make this device the amplifier of choice for general- a wide frequency range, making it an ideal driver for high speed purpose IF and broadband applications where low distortion, 8-bit to 16-bit ADCs. noise, and power are critical. This device is optimized for the best combination of slew speed, bandwidth, and broadband The ADL5562 provides three gain levels of 6 dB, 12 dB, and distortion. These attributes allow it to drive a wide variety of 15.5 dB through a pin-strappable configuration. For the single- analog-to-digital converters (ADCs) and make it ideally suited ended input configuration, the gains are reduced to 5.6 dB, for driving mixers, pin diode attenuators, SAW filters, and 11.1 dB, and 14.1 dB. Using an external series input resistor multi-element discrete devices. expands the amplifier gain flexibility and allows for any gain selection from 0 dB to 15.5 dB. Fabricated on an Analog Devices, Inc., high speed SiGe process, the ADL5562 is supplied in a compact 3 mm 3 mm, 16-lead The quiescent current of the ADL5562 is typically 80 mA and, LFCSP package and operates over the temperature range of when disabled, consumes less than 3 mA, offering excellent 40C to + 85C. input-to-output isolation. Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20092017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 08003-001ADL5562 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Basic Structure ............................................................................ 13 Applications ....................................................................................... 1 Applications Information .............................................................. 14 Functional Block Diagram .............................................................. 1 Basic Connections ...................................................................... 14 General Description ......................................................................... 1 Input and Output Interfacing ................................................... 15 Revision History ............................................................................... 2 Gain Adjustment and Interfacing ............................................ 16 Specifications ..................................................................................... 3 ADC Interfacing ......................................................................... 16 Absolute Maximum Ratings ............................................................ 6 Layout Considerations ............................................................... 18 ESD Caution .................................................................................. 6 Soldering Information ............................................................... 19 Pin Configuration and Function Descriptions ............................. 7 Evaluation Board ........................................................................ 19 Typical Performance Characteristics ............................................. 8 Outline Dimensions ....................................................................... 21 Circuit Description ......................................................................... 13 Ordering Guide .......................................................................... 21 REVISION HISTORY 9/2017Rev. E to Rev. F 3/2010Rev. A to Rev. B Updated Outline Dimensions ....................................................... 21 Changes to Figure 43 ...................................................................... 19 Changes to Ordering Guide .......................................................... 21 Updated Outline Dimensions ....................................................... 21 Changes to Ordering Guide .......................................................... 21 1/2014Rev. D to Rev. E Changes to ENBL Threshold Parameter, Table 1 ......................... 3 9/2009Rev. 0 to Rev. A Changes to Features Section ............................................................ 1 4/2013Rev. C to Rev. D Changes to Table 1 ............................................................................. 3 Changes to Table 1 ............................................................................ 3 Changes to Figure 5 ........................................................................... 8 Changes to Figure 6 and Figure 7 ................................................... 8 Changes to Figure 9 and Figure 10 .................................................. 9 Changes to Figure 32, Equation 1, and Figure 34 ...................... 15 Changes to Equation 2 ................................................................... 16 7/2011Rev. B to Rev. C Changes to Figure 38, Figure 39, Figure 40, and Table 9........... 17 Changes to Figure 28 and Figure 29 ............................................. 12 Changes to Figure 43 ...................................................................... 19 Added Figure 30 and Figure 31 Renumbered Sequentially ..... 12 Moved Table 14 to .......................................................................... 19 Changes to Ordering Guide .......................................................... 21 5/2009Revision 0: Initial Version Rev. F Page 2 of 21