6.5 GHz, Ultrahigh Dynamic Range, Differential Amplifier Data Sheet ADL5569 FEATURES FUNCTIONAL BLOCK DIAGRAM PDB VCOM VCC 3 dB bandwidth: 6.5 GHz typical 16 15 14 Preset 20 dB voltage gain, can be reduced by adding ADL5569 external resistors Differential or single-ended input to differential output R R G F Internally dc-coupled inputs and outputs 1 13 VON VIN 500 50 Low noise input stage: 9.3 dB noise figure at 2 GHz B GM R R Low distortion at 5 V supply and 2 V p-p output with 100 load G F 2 12 VIP VOP 500 50 500 MHz: 78 dBc (HD2), 71 dBc (HD3), 80 dBc (IMD3) 2 GHz: 64 dBc (HD2), 52 dBc (HD3), 65 dBc (IMD3) Input voltage noise (NSD, RTI): 1.0 nV/Hz at 100 MHz 3 11 GND GND Single-supply operation: ac-coupled applications Dual-supply operation: dc-coupled applications Slew rate: 24 V/ns at 2 V p-p output R R G F 4 10 VOP2 VIP2 DC power consumption: 86 mA per amplifier at 5 V 500 50 B GM R R APPLICATIONS G F VIN2 5 9 VON2 50 500 Differential ADC drivers for GSPS ADCs High speed data acquisition Single-ended to differential conversion DAC buffering 6 7 8 PDB2 VCOM2 VCC2 DC coupling and level shifting NOTES RF/IF gain blocks 1. R IS THE SERIES RESISTANCE OF THE AMPLIFIER, G AND R IS THE FEEDBACK RESISTANCE F Balun alternative from dc to 4 GHz OF THE AMPLIFIER. SAW filter interfacing Figure 1. GENERAL DESCRIPTION The ADL5569 is a high performance, dual, differential amplifier 3.0 V, providing a flexible capability for driving ADCs with with 20 dB of voltage gain, optimized for applications spanning ac levels up to 2 V p-p. from dc to 6.5 GHz. The amplifier is available in a dual format, Operating from a single 5 V supply, the quiescent current of the and it offers a low referred to input (RTI) noise spectral density ADL5569 is typically 86 mA per amplifier. When disabled, the (NSD) of 1.0 nV/Hz (at 100 MHz) and excellent distortion amplifiers consume only 8 mA per amplifier. performance over a wide frequency range, making it an ideal The device is optimized for wideband, low distortion, and low driver for high speed 12-bit to 16-bit analog-to-digital converters noise operation, giving it unprecedented second harmonic (ADCs). The ADL5569 is ideally suited for use in high perfor- distortion (HD2) and third harmonic distortion (HD3) from mance zero intermediate frequency (IF) and complex IF receiver dc to 4 GHz. These attributes, together with its adjustable gain designs. In addition, this device has excellent low distortion for capability, make this device the amplifier of choice for driving a single-ended input driver applications. wide variety of ADCs, mixers, pin diode attenuators, surface Using two external series resistors for each amplifier expands acoustic wave (SAW) filters, and a multitude of discrete radio the gain flexibility of the amplifier and allows any gain selection frequency (RF) devices. from 6 dB to 20 dB for a differential input. For a single-ended Fabricated on an Analog Devices, Inc., high speed silicon germa- input, the gain can be adjusted from 6 dB to 17 dB with the nium (SiGe) process, the ADL5569 is supplied in a compact addition of some external resistors. This device maintains low 2.5 mm 3 mm, 16-lead LFCSP package and operates over the distortion through its output common-mode range of 2.0 V to 40C to +85C temperature range. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 2018 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 15671-001ADL5569 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Applications Information .............................................................. 15 Applications ....................................................................................... 1 Basic Connections ...................................................................... 15 Functional Block Diagram .............................................................. 1 Input and Output Interfacing ................................................... 16 General Description ......................................................................... 1 Gain Adjustment and Interfacing ............................................ 17 Revision History ............................................................................... 2 Effect of Load Capacitance ....................................................... 18 Specifications ..................................................................................... 3 GSPS ADC Interfacing .............................................................. 18 Absolute Maximum Ratings ............................................................ 6 Soldering Information and Recommended Land Pattern .... 20 Thermal Resistance ...................................................................... 6 Evaluation Board ........................................................................ 20 ESD Caution .................................................................................. 6 Outline Dimensions ....................................................................... 23 Pin Configuration and Function Descriptions ............................. 7 Ordering Guide .......................................................................... 23 Typical Performance Characteristics ............................................. 8 Theory of Operation ...................................................................... 14 REVISION HISTORY 11/2018Rev. B to Rev. C Changes to GSPS ADC Interfacing Section ................................ 18 Updated Outline Dimensions ....................................................... 23 8/2018Rev. A to Rev. B Changes to Gain Adjustment and Interfacing Section .............. 17 7/2018Rev. 0 to Rev. A Changes to Figure 4 and Figure 7 ................................................... 8 Changes to Figure 10, Figure 11, Figure 12, and Figure 13 ......... 9 Changes to Figure 19 and Figure 20 Captions ............................ 10 Changes to Figure 23 and Figure 24 ............................................. 11 5/2018Revision 0: Initial Version Rev. C Page 2 of 23