High IP3, 700 MHz to 2800 MHz, Double Balanced, Passive Mixer, IF Amplifier, and Wideband LO Amplifier Data Sheet ADL5811 FEATURES FUNCTIONAL BLOCK DIAGRAM RF frequency: 700 MHz to 2800 MHz continuous LO frequency: 250 MHz to 2800 MHz, high-side or 32 31 30 29 28 27 26 25 low-side inject 1 24 NC NC IF range: 30 MHz to 450 MHz RFCT 2 23 NC Power conversion gain of 7.5 dB at 1900 MHz ADL5811 NC 3 22 NC SSB noise figure of 10.7 dB at 1900 MHz RFIN 4 21 LOIP Input IP3 of 27.5 dBm at 1900 MHz Input P1dB of 12.7 dBm at 1900 MHz 5 20 NC LOIN Typical LO drive of 0 dBm 6 19 NC LE SERIAL Single-ended, 50 RF port BIAS NC 7 PORT 18 DATA GEN INTERFACE Single-ended or balanced LO input port NC 8 17 CLK Single-supply operation: 3.6 V to 5.0 V 9 10 11 12 13 14 15 16 Serial port interface control on all functions Exposed paddle 5 mm 5 mm, 32-lead LFCSP package Figure 1. APPLICATIONS Multiband/multistandard cellular base station receivers Wideband radio link diversity downconverters Multimode cellular extenders and broadband receivers GENERAL DESCRIPTION The ADL5811 uses revolutionary new broadband, square wideband applications where in-band blocking signals may wave limiting, local oscillator (LO) amplifiers to achieve an otherwise result in the degradation of dynamic range. Blocker unprecedented radio frequency (RF) bandwidth of 700 MHz noise figure performance is comparable to narrow-band passive to 2800 MHz. Unlike conventional narrow-band sine wave LO mixer designs. High linearity IF buffer amplifiers follow the amplifier solutions, this permits the LO to be applied either passive mixer cores, yielding typical power conversion gains of above or below the RF input over an extremely wide bandwidth. 7.5 dB, and can be used with a wide range of output Because energy storage elements are not used, the dc current impedances. For low voltage applications, the ADL5811 is consumption also decreases with decreasing LO frequency. capable of operation at voltages down to 3.6 V with substantially reduced current. Two logic bits are provided to The ADL5811 uses highly linear, doubly balanced, passive power down (<1.5 mA) the circuit when desired. mixer cores along with integrated RF and LO balancing circuits to allow single-ended operation. The ADL5811 incorporates All features of the ADL5811 are controlled via a 3-wire serial programmable RF baluns, allowing optimal performance over a port interface, resulting in optimum performance and 700 MHz to 2800 MHz RF input frequency. The balanced passive minimum external components. mixer arrangement provides outstanding LO-to-RF and LO-to- The ADL5811 is fabricated using a BiCMOS high performance IF leakages, excellent RF-to-IF isolation, and excellent IC process. The device is available in a 32-lead, 5mm 5mm, intermodulation performance over the full RF bandwidth. LFCSP package and operates over a 40C to +85C The balanced mixer cores also provide extremely high input temperature range. An evaluation board is also available. linearity, allowing the device to be used in demanding Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20112017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com VLO4 VPIF COMM IFGM VLO3 NC COMM IFOP VLO2 IFON COMM NC VLO1 IFGD COMM COMM 09912-001ADL5811 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 RF Subsystem .............................................................................. 20 Applications ....................................................................................... 1 LO Subsystem ............................................................................. 21 Functional Block Diagram .............................................................. 1 Applications Information .............................................................. 22 General Description ......................................................................... 1 Basic Connections ...................................................................... 22 Revision History ............................................................................... 2 IF Port .......................................................................................... 22 Specifications ..................................................................................... 3 Bias Resistor Selection ............................................................... 22 Timing Characteristics ................................................................ 4 VGS Programming ..................................................................... 22 Absolute Maximum Ratings ............................................................ 5 Low-Pass Filter Programming .................................................. 23 ESD Caution .................................................................................. 5 RF Balun Programming ............................................................ 23 Pin Configuration and Function Descriptions ............................. 6 Register Structure ........................................................................... 24 Typical Performance Characteristics ............................................. 7 Evaluation Board ............................................................................ 25 3.6 V Performance ...................................................................... 16 Outline Dimensions ....................................................................... 28 Spurious Performance................................................................ 17 Ordering Guide .......................................................................... 28 Circuit Description ......................................................................... 20 REVISION HISTORY 3/2017Rev. 0 to Rev. A Changed CP-32-13 to CP-32-20 .................................. Throughout Changes to Figure 1 .......................................................................... 1 Changes to Figure 3 .......................................................................... 6 Changes to Figure 58 ...................................................................... 20 Updated Outline Dimensions ....................................................... 28 Changes to Ordering Guide .......................................................... 28 7/2011Revision 0: Initial Version Rev. A Page 2 of 28