Dual High IP3, 700 MHz to 2800 MHz, Double Balanced, Passive Mixer, IF Amplifier, and Wideband LO Amplifier ADL5812 FEATURES FUNCTIONAL BLOCK DIAGRAM RF frequency: 700 MHz to 2800 MHz continuous LO frequency: 250 MHz to 2800 MHz, high-side or 40 39 38 37 36 35 34 33 32 31 low-side inject RF1 1 30 V1LO1 IF range: 30 MHz to 450 MHz RFCT1 2 29 NC Power conversion gain of 6.7 dB at 1900 MHz ADL5812 NC 3 28 NC SSB noise figure of 11.6 dB at 1900 MHz Input IP3 of 27.2 dBm at 1900 MHz NC 4 27 NC Input P1dB of 12.5 dBm at 1900 MHz NC 5 26 LOIP BIAS Typical LO drive of 0 dBm GEN NC 6 25 LOIN Single-ended, 50 RF port NC 7 24 LE Single-ended or balanced LO input port NC 8 23 DATA SERIAL Single-supply operation: 3.6 V to 5.0 V PORT RFCT2 9 22 CLK INTERFACE Serial port interface control on all functions RF2 10 21 V2LO1 Exposed paddle 6 mm 6 mm, 40-lead LFCSP package 11 12 13 14 15 16 17 18 19 20 APPLICATIONS Figure 1. Multiband/multistandard cellular base station diversity receivers Wideband radio link diversity downconverters Multimode cellular extenders and broadband receivers GENERAL DESCRIPTION The ADL5812 uses revolutionary new broadband, square wave wideband applications where in-band blocking signals may limiting, local oscillator (LO) amplifiers to achieve an otherwise result in the degradation of dynamic range. Blocker unprecedented radio frequency (RF) bandwidth of 700 MHz noise figure performance is comparable to narrow-band passive to 2800 MHz. Unlike conventional narrow-band sine wave LO mixer designs. High linearity IF buffer amplifiers follow the amplifier solutions, this permits the LO to be applied either passive mixer cores, yielding typical power conversion gains of above or below the RF input over an extremely wide bandwidth. 6.7 dB, and can be used with a wide range of output Because energy storage elements are not used, the dc current impedances. For low voltage applications, the ADL5812 is consumption also decreases with decreasing LO frequency. capable of operation at voltages down to 3.6 V with substantially reduced current. Two logic bits are provided to The ADL5812 uses highly linear, doubly balanced, passive mixer individually power down (1.5 mA for both channels) the two cores along with integrated RF and LO balancing circuits to channels as desired. allow single-ended operation. The ADL5812 incorporates programmable RF baluns, allowing optimal performance over All features of the ADL5812 are controlled via a 3-wire serial a 700 MHz to 2800 MHz RF input frequency. The balanced port interface, resulting in optimum performance and passive mixer arrangement provides outstanding LO-to-RF and minimum external components. LO-to-IF leakages, excellent RF-to-IF isolation, and excellent The ADL5812 is fabricated using a BiCMOS high performance intermodulation performance over the full RF bandwidth. IC process. The device is available in a 40-lead, 6mm 6mm, The balanced mixer cores also provide extremely high input LFCSP package and operates over a 40C to +85C linearity, allowing the device to be used in demanding temperature range. An evaluation board is also available. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. VPIF2 VPIF1 IFGM2 IFGM1 NC NC IFOP2 IFOP1 IFON2 IFON1 NC NC IFGD2 IFGD1 V2LO4 V1LO4 V2LO3 V1LO3 V2LO2 V1LO2 09913-001ADL5812 TABLE OF CONTENTS Features .............................................................................................. 1 RF Subsystem.............................................................................. 20 Applications....................................................................................... 1 LO Subsystem ............................................................................. 21 Functional Block Diagram .............................................................. 1 Applications Information .............................................................. 22 General Description ......................................................................... 1 Basic Connections...................................................................... 22 Revision History ............................................................................... 2 IF Port .......................................................................................... 22 Specifications..................................................................................... 3 Bias Resistor Selection ............................................................... 22 Timing Characteristics ................................................................ 4 VGS Programming..................................................................... 23 Absolute Maximum Ratings............................................................ 5 Low-Pass Filter Programming.................................................. 23 ESD Caution.................................................................................. 5 RF Balun Programming ............................................................ 23 Pin Configuration and Function Descriptions............................. 6 Register Structure ........................................................................... 24 Typical Performance Characteristics ............................................. 7 Evaluation Board ............................................................................ 25 3.6 V Performance...................................................................... 16 Outline Dimensions....................................................................... 27 Spurious Performance................................................................ 17 Ordering Guide .......................................................................... 27 Circuit Description......................................................................... 20 REVISION HISTORY 7/11Revision 0: Initial Version Rev. 0 Page 2 of 28