ADM1067ACPZ Analog Devices

Super Sequencer with Open-Loop Margining DACs Data Sheet ADM1067 FEATURES FUNCTIONAL BLOCK DIAGRAM REFOUT REFGND SDA SCL A1 A0 Complete supervisory and sequencing solution for up to 10 supplies SMBus ADM1067 VREF EEPROM INTERFACE 10 supply fault detectors enable supervision of supplies to <0.5% accuracy at all voltages at 25C VX1 PDO1 CONFIGURABLE <1.0% accuracy across all voltages and temperatures DUAL- OUTPUT PDO2 VX2 FUNCTION DRIVERS INPUTS PDO3 5 selectable input attenuators allow supervision of supplies to VX3 PDO4 (LOGIC INPUTS (HV CAPABLE OF 14.4 V on VH VX4 OR DRIVING GATES PDO5 SFDs) OF N-FET) VX5 PDO6 6 V on VP1 to VP4 (VPx) SEQUENCING ENGINE 5 dual-function inputs, VX1 to VX5 (VXx) VP1 PDO7 CONFIGURABLE OUTPUT PROGRAMMABLE High impedance input to supply fault detector with VP2 RESET DRIVERS PDO8 GENERATORS VP3 thresholds between 0.573 V and 1.375 V (LV CAPABLE PDO9 (SFDs) OF DRIVING VP4 LOGIC SIGNALS) General-purpose logic input VH PDO10 10 programmable driver outputs, PDO1 to PDO10 (PDOx) AGND PDOGND Open-collector with external pull-up GND VDD VDDCAP ARBITRATOR VCCP Push/pull output, driven to VDDCAP or VPx MDN Open collector with weak pull-up to VDDCAP or VPx MUP V V V V V V Internally charge-pumped high drive for use with external OUT OUT OUT OUT OUT OUT DAC DAC DAC DAC DAC DAC N-FET (PDO1 to PDO6 only) Sequencing engine (SE) implements state machine control of DAC1 DAC2 DAC3 DAC4 DAC5 DAC6 PDO outputs Figure 1. State changes conditional on input events GENERAL DESCRIPTION Enables complex control of boards Power-up and power-down sequence control The ADM1067 Super Sequencer is a configurable supervisory/ Fault event handling sequencing device that offers a single-chip solution for supply Interrupt generation on warnings monitoring and sequencing in multiple supply systems. In addition Watchdog function can be integrated in SE to these functions, the ADM1067 integrates six 8-bit voltage Program software control of sequencing through SMBus output DACs. These circuits can be used to implement an open- Open-loop margining solution for 6 voltage rails loop margining system that enables supply adjustment by altering 6 voltage output 8-bit DACs (0.300 V to 1.551 V) allow voltage either the feedback node or reference of a dc-to-dc converter adjustment via dc-to-dc converter trim/feedback node using the DAC outputs. Device powered by the highest of VPx, VH for improved For more information about the ADM1067 register map, refer redundancy to the AN-698 Application Note. User EEPROM: 256 bytes Industry-standard 2-wire bus interface (SMBus) Guaranteed PDO low with VH, VPx = 1.2 V Available in 40-lead, 6 mm 6 mm LFCSP and 48-lead, 7 mm 7 mm TQFP packages APPLICATIONS Central office systems Servers/routers Multivoltage system line cards DSP/FPGA supply sequencing In-circuit testing of margined supplies Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20042015 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 04635-001ADM1067 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Overview ..................................................................................... 18 Applications ....................................................................................... 1 Warnings...................................................................................... 18 Functional Block Diagram .............................................................. 1 SMBus Jump (Unconditional Jump) ........................................ 18 General Description ......................................................................... 1 Sequencing Engine Application Example ............................... 19 Revision History ............................................................................... 3 Fault and Status Reporting ........................................................ 20 Detailed Block Diagram .................................................................. 4 Supply Margining ........................................................................... 21 Specif icat ions ..................................................................................... 5 Overview ..................................................................................... 21 Absolute Maximum Ratings ............................................................ 8 Open-Loop Supply Margining ................................................. 21 Thermal Resistance ...................................................................... 8 Writing to the DACs .................................................................. 21 ESD Caution .................................................................................. 8 Choosing the Size of the Attenuation Resistor ....................... 22 Pin Configurations and Function Descriptions ........................... 9 DAC Limiting and Other Safety Features ............................... 22 Typical Performance Characteristics ........................................... 11 Applications Diagram .................................................................... 23 Powering the ADM1067 ................................................................ 14 Communicating with the ADM1067 ........................................... 24 Slew Rate Consideration ............................................................ 14 Configuration Download at Power-Up ................................... 24 Inputs ................................................................................................ 15 Updating the Configuration ..................................................... 24 Supply Supervision ..................................................................... 15 Updating the Sequencing Engine ............................................. 25 Programming the Supply Fault Detectors ............................... 15 Internal Registers ........................................................................ 25 Input Comparator Hysteresis .................................................... 15 EEPROM ..................................................................................... 25 Input Glitch Filtering ................................................................. 16 Serial Bus Interface ..................................................................... 25 Supply Supervision with VXx Inputs ....................................... 16 SMBus Protocols for RAM and EEPROM .............................. 28 VXx Pins as Digital Inputs ........................................................ 16 Write Operations ........................................................................ 28 Outputs ............................................................................................ 17 Read Operations ......................................................................... 30 Supply Sequencing Through Configurable Output Drivers ....... 17 Outline Dimensions ....................................................................... 31 Default Output Configuration .................................................. 17 Ordering Guide .......................................................................... 31 Sequencing Engine ......................................................................... 18 Rev. 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