ADM1169ASTZ Analog Devices

Super Sequencer with Margining Control and Nonvolatile Fault Recording Data Sheet ADM1169 FEATURES FUNCTIONAL BLOCK DIAGRAM REFIN REFOUT REFGND SDA SCL A1 A0 Complete supervisory and sequencing solution for up to 8 supplies ADM1169 VREF SMBus 16-event deep black box nonvolatile fault recording INTERFACE 8 supply fault detectors enable supervision of supplies to 12-BIT SAR ADC <0.5% accuracy at all voltages at 25C FAULT EEPROM <1.0% accuracy across all voltages and temperatures RECORDING CLOSED-LOOP MARGINING SYSTEM 4 selectable input attenuators allow supervision of supplies to PDO1 CONFIGURABLE 14.4 V on VH and 6 V on VP1 to VP3 (VPx) DUAL- OUTPUT PDO2 VX1 FUNCTION DRIVERS INPUTS 4 dual-function inputs, VX1 to VX4 (VXx) PDO3 VX2 PDO4 (LOGIC INPUTS (HV CAPABLE OF High impedance input to supply fault detector with VX3 OR PDO5 DRIVING GATES SFDs) OF NFET) VX4 PDO6 thresholds between 0.573 V and 1.375 V SEQUENCING ENGINE General-purpose logic input VP1 CONFIGURABLE 8 programmable driver outputs, PDO1 to PDO8 (PDOx) OUTPUT PROGRAMMABLE VP2 DRIVERS RESET PDO7 GENERATORS Open-collector with external pull-up VP3 (LV CAPABLE PDO8 OF DRIVING (SFDs) VH Push/pull output, driven to VDDCAP or VPx LOGIC SIGNALS) Open-collector with weak pull-up to VDDCAP or VPx AGND PDOGND Internally charge-pumped high drive for use with external VDD V V V V VDDCAP OUT OUT OUT OUT ARBITRATOR DAC DAC DAC DAC NFET (PDO1 to PDO6 only) SE implements state machine control of PDO outputs DAC1 DAC2 DAC3 DAC4 VCCP GND State changes conditional on input events Figure 1. Enables complex control of boards Power-up and power-down sequence control GENERAL DESCRIPTION Fault event handling The ADM1169 Super Sequencer is a configurable supervisory/ Interrupt generation on warnings sequencing device that offers a single-chip solution for supply Watchdog function can be integrated in SE monitoring and sequencing in multiple supply systems. In addition Program software control of sequencing through SMBus to these functions, the ADM1169 integrates a 12-bit ADC and Complete voltage margining solution for 4 voltage rails four 8-bit voltage output DACs. These circuits can be used to 4 voltage output 8-bit DACs (0.300 V to 1.551 V) allow voltage implement a closed-loop margining system that enables supply adjustment via dc-to-dc converter trim/feedback node adjustment by altering either the feedback node or reference of 12-bit ADC for readback of all supervised voltages a dc-to-dc converter using the DAC outputs. Reference input (REFIN) has 2 input options Supply margining can be performed with a minimum of external Driven directly from 2.048 V (0.25%) REFOUT pin components. The margining loop can be used for in-circuit More accurate external reference for improved ADC testing of a board during production (for example, to verify performance board functionality at 5% of nominal supplies), or it can be Device powered by the highest of VPx, VH for improved used dynamically to accurately control the output voltage of redundancy a dc-to-dc converter. User EEPROM: 256 bytes Industry-standard 2-wire bus interface (SMBus) For more information about the ADM1169 register map, refer Guaranteed PDO low with VH, VPx = 1.2 V to the AN-721 Application Note. Available in 32-lead LQFP and 40-lead LFCSP packages APPLICATIONS Central office systems Servers/routers Multivoltage system line cards DSP/FPGA supply sequencing In-circuit testing of margined supplies Rev. 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MUX 09475-001ADM1169 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Sequencing Engine Application Example ............................... 19 Applications ....................................................................................... 1 Fault and Status Reporting ........................................................ 20 Functional Block Diagram .............................................................. 1 Nonvolatile Black Box Fault Recording ................................... 20 General Description ......................................................................... 1 Black Box Writes with No External Supply ............................ 21 Revision History ............................................................................... 2 Voltage Readback............................................................................ 22 Detailed Block Diagram .................................................................. 3 Supply Supervision with the ADC ........................................... 22 Specif icat ions ..................................................................................... 4 Supply Margining ........................................................................... 23 Absolute Maximum Ratings ............................................................ 7 Overview ..................................................................................... 23 Thermal Resistance ...................................................................... 7 Open-Loop Supply Margining ................................................. 23 ESD Caution .................................................................................. 7 Closed-Loop Supply Margining ............................................... 23 Pin Configurations and Function Descriptions ........................... 8 Writing to the DACs .................................................................. 24 Typical Performance Characteristics ........................................... 10 Choosing the Size of the Attenuation Resistor ....................... 24 Powering the ADM1169 ................................................................ 13 DAC Limiting and Other Safety Features ............................... 24 Slew Rate Consideration ............................................................ 13 Applications Diagram .................................................................... 25 Inputs ................................................................................................ 14 Communicating with the ADM1169 ........................................... 26 Supply Supervision ..................................................................... 14 Configuration Download at Power-Up ................................... 26 Programming the Supply Fault Detectors ............................... 14 Updating the Configuration ..................................................... 26 Input Comparator Hysteresis .................................................... 15 Updating the Sequencing Engine ............................................. 27 Input Glitch Filtering ................................................................. 15 Internal Registers ........................................................................ 27 Supply Supervision with VXx Inputs ....................................... 16 EEPROM ..................................................................................... 27 VXx Pins as Digital Inputs ........................................................ 16 Serial Bus Interface ..................................................................... 28 Outputs ............................................................................................ 17 SMBus Protocols for RAM and EEPROM .............................. 29 Supply Sequencing Through Configurable Output Drivers ....... 17 Write Operations ........................................................................ 30 Default Output Configuration .................................................. 17 Read Operations ......................................................................... 31 Sequencing Engine ......................................................................... 18 Outline Dimensions ....................................................................... 33 O ver vie w ...................................................................................... 18 Ordering Guide .......................................................................... 33 Warnings ...................................................................................... 18 SMBus Jump (Unconditional Jump) ........................................ 18 REVISION HISTORY 1/15Rev. A to Rev. B Changes to Table 4 ............................................................................ 8 Added Slew Rate Consideration Section ..................................... 13 8/13Rev. 0 to Rev. A Change to Table 12 ......................................................................... 28 4/11Revision 0: Initial Version Rev. B Page 2 of 33