5 V Low Power a EIA RS-485 Transceiver ADM485 FEATURES FUNCTIONAL BLOCK DIAGRAM Meets EIA RS-485 Standard 5 Mbps Data Rate Single 5 V Supply ADM485 7 V to +12 V Bus Common-Mode Range High Speed, Low Power BiCMOS RO R V CC Thermal Shutdown Protection Short-Circuit Protection RE B Driver Propagation Delay: 10 ns Receiver Propagation Delay: 15 ns DE A High Z Outputs with Power Off Superior Upgrade for LTC485 DI D GND APPLICATIONS Low Power RS-485 Systems DTE-DCE Interface Packet Switching Local Area Networks Data Concentration Data Multiplexers Integrated Services Digital Network (ISDN) GENERAL DESCRIPTION This minimizes the loading effect when the transceiver is not being The ADM485 is a differential line transceiver suitable for high used. The high impedance driver output is maintained over the speed bidirectional data communication on multipoint bus trans- entire common-mode voltage range from 7 V to +12 V. mission lines. It is designed for balanced data transmission and The receiver contains a fail-safe feature that results in a logic complies with EIA Standards RS-485 and RS-422. The part high output state if the inputs are unconnected (floating). contains a differential line driver and a differential line receiver. The ADM485 is fabricated on BiCMOS, an advanced mixed Both the driver and the receiver may be enabled independently. technology process combining low power CMOS with fast switching When disabled, the outputs are three-stated. bipolar technology. All inputs and outputs contain protection The ADM485 operates from a single 5 V power supply. Excessive against ESD all driver outputs feature high source and sink current power dissipation caused by bus contention or by output shorting capability. An epitaxial layer is used to guard against latch-up. is prevented by a thermal shutdown circuit. This feature forces The ADM485 features extremely fast switching speeds. Minimal the driver output into a high impedance state if during fault condi- driver propagation delays permit transmission at data rates up to tions a significant temperature increase is detected in the internal 5 Mbps while low skew minimizes EMI interference. driver circuitry. The part is fully specified over the commercial and industrial Up to 32 transceivers may be connected simultaneously on a bus, temperature range and is available in PDIP, SOIC, and small but only one driver should be enabled at any time. It is important, footprint MSOP packages. therefore, that the remaining disabled drivers do not load the bus. To ensure this, the ADM485 driver features high output imped- ance when disabled and when powered down. REV. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700 www.analog.com under any patent or patent rights of Analog Devices. Trademarks and Fax: 781/326-8703 2003 Analog Devices, Inc. All rights reserved. registered trademarks are the property of their respective owners.ADM485SPECIFICATIONS (V = 5 V 5%. All specifications T to T , unless otherwise noted.) CC MIN MAX Parameter Min Typ Max Unit Test Conditions/Comments DRIVER Differential Output Voltage, V 5.0 V R = , Test Circuit 1 OD 2.0 5.0 V V = 5 V, R = 50 (RS-422), Test Circuit 1 CC 1.5 5.0 V R = 27 (RS-485), Test Circuit 1 V 1.5 5.0 V V = 7 V to +12 V, Test Circuit 2 OD3 TST V for Complementary Output States 0.2 V R = 27 or 50 , Test Circuit 1 OD Common-Mode Output Voltage, V 3V R = 27 or 50 , Test Circuit 1 OC V for Complementary Output States 0.2 V R = 27 or 50 OD Output Short-Circuit Current (V = High) 35 250 mA 7 V V +12 V OUT O Output Short-Circuit Current (V = Low) 35 250 mA 7 V V +12 V OUT O CMOS Input Logic Threshold Low, V 0.8 V INL CMOS Input Logic Threshold High, V 2.0 V INH Logic Input Current (DE, DI) 1.0 A RECEIVER Differential Input Threshold Voltage, V 0.2 +0.2 V 7 V V +12 V TH CM Input Voltage Hysteresis, V 70 mV V = 0 V TH CM Input Resistance 12 k 7 V V +12 V CM Input Current (A, B) 1 mA V = 12 V IN 0.8 mA V = 7 V IN CMOS Input Logic Threshold Low, V 0.8 V INL CMOS Input Logic Threshold High, V 2.0 V INH Logic Enable Input Current (RE) 1 A CMOS Output Voltage Low, V 0.4 V I = +4.0 mA OL OUT CMOS Output Voltage High, V 4.0 V I = 4.0 mA OH OUT Short-Circuit Output Current 7 85 mA V = GND or V OUT CC Three-State Output Leakage Current 1.0 A 0.4 V V 2.4 V OUT POWER SUPPLY CURRENT I (Outputs Enabled) 1.0 2.2 mA Digital Inputs = GND or V CC CC I (Outputs Disabled) 0.6 1 mA Digital Inputs = GND or V CC CC Specifications subject to change without notice. (V = 5 V 5%. All specifications T to T , unless otherwise noted.) TIMING SPECIFICATIONS CC MIN MAX Parameter Min Typ Max Unit Test Conditions/Comments DRIVER Propagation Delay Input to Output t , t 210 15 ns R = 54 , C = C = 100 pF, Test Circuit 3 PLH PHL LDIFF L1 L2 15 ns R = 54 , C = C = 100 pF, Test Circuit 3 Driver O/P to O/P, t SKEW LDIFF L1 L2 Driver Rise/Fall Time, t , t 815 ns R = 54 , C = C = 100 pF, Test Circuit 3 R F LDIFF L1 L2 Driver Enable to Output Valid 10 25 ns R = 110 , C = 50 pF, Test Circuit 4 L L = 110 , C = 50 pF, Test Circuit 4 Driver Disable Timing 10 25 ns R L L Matched Enable Switching 0 2 ns R = 110 , C = 50 pF, Test Circuit 4* L L t t , t t AZH BZL BZH AZL = 110 , C = 50 pF, Test Circuit 4* Matched Disable Switching 0 2 ns R L L t t , t t AHZ BLZ BHZ ALZ RECEIVER Propagation Delay Input to Output, t , t 815 30 ns C = 15 pF, Test Circuit 5 PLH PHL L Skew t t 5nsC = 15 pF, Test Circuit 5 PLH PHL L Receiver Enable, t 520 ns C = 15 pF, R = 1 k , Test Circuit 6 EN1 L L Receiver Disable, t 520 ns C = 15 pF, R = 1 k , Test Circuit 6 EN2 L L Tx Pulse Width Distortion 1 ns Rx Pulse Width Distortion 1 ns *Guaranteed by characterization. Specifications subject to change without notice. 2 REV. E