600 mA, Ultralow Noise, High PSRR, RF Linear Regulator Data Sheet ADM7154 FEATURES TYPICAL APPLICATION CIRCUIT Input voltage range: 2.3 V to 5.5 V ADM7154 V = 3.8V V = 3.3V IN OUT Maximum load current: 600 mA VIN VOUT C C IN OUT Low noise 10F 10F ON 0.9 V rms total integrated noise from 100 Hz to 100 kHz EN REF C REF 1.6 V rms total integrated noise from 10 Hz to 100 kHz OFF 1F REF SENSE BYP C Noise spectral density: 1.5 nV/Hz from 10 kHz to 1 MHz BYP 1F PSRR of 90 dB from 200 Hz to 200 kHz 58 dB at 1 MHz, VREG C V = 3.3 V, V = 3.8 V REG OUT IN GND 10F Dropout voltage: 120 mV typical at V = 3.3 V, I = 600 mA OUT OUT Initial accuracy: 0.5% Figure 1. Regulated 3.3 V Output from 3.8 V Input Accuracy over line, load, and temperature: 2.0% (minimum), 10k +1.5% (maximum), from 40C to +85C NOISE FLOOR 1.0F Quiescent current, I = 4 mA at no load GND 3.3F Low shutdown current: 0.2 A 1k 10F 33F Stable with a 10 F ceramic output capacitor 100F 330F Adjustable and fixed output voltage options: 1.2 V, 1.8 V, 2.5 V, 100 1000F 2.8 V, 3.0 V, 3.3 V (16 standard voltages between 1.2 V and 3.3 V available) 10 8-lead LFCSP and 8-lead SOIC packages Precision enable Supported by ADIsimPower tool 1 APPLICATIONS 0.1 Regulation to noise sensitive applications: PLLs, VCOs, and 0.1 1 10 100 1k 10k 100k 1M PLLs with integrated VCOs FREQUENCY (Hz) Communications and infrastructure Figure 2. Noise Spectral Density for Different Values of CBYP Backhaul and microwave links GENERAL DESCRIPTION The ADM7154 is a linear regulator that operates from 2.3 V to The ADM7154 is available in 8-lead, 3 mm 3 mm LFCSP and 5.5 V and provides up to 600 mA of load current. Using an 8-lead SOIC packages, making it not only a very compact advanced proprietary architecture, it provides high power solution, but also providing excellent thermal performance for supply rejection and ultralow noise, achieving excellent line and applications requiring up to 600 mA of load current in a small, load transient response with only a 10 F ceramic output capacitor. low profile footprint. There are 16 standard output voltages for the ADM7154. The Table 1. Related Devices following voltages are available in stock: 1.2 V, 1.8 V, 2.5 V, 2.8 V, Input Output Fixed/ 1 3.0 V, and 3.3 V. Additional voltages are available by special Model Voltage Current Adj Package order: 1.3 V, 1.5 V, 1.6 V, 2.0 V, 2.2 V, 2.6 V, 2.7 V, 2.9 V, 3.1 V, ADM7150ACP 4.5 V to 16 V 800 mA Fixed 8-Lead LFCSP and 3.2 V. ADM7150ARD 4.5 V to 16 V 800 mA Fixed 8-Lead SOIC ADM7151ACP 4.5 V to 16 V 800 mA Adj 8-Lead LFCSP The ADM7154 regulator typical output noise is 0.9 V rms from ADM7151ARD 4.5 V to 16 V 800 mA Adj 8-Lead SOIC 100 Hz to 100 kHz for fixed output voltage options and ADM7155ACP 2.3 V to 5.5 V 600 mA Adj 8-Lead LFCSP 1.5 nV/Hz for noise spectral density from 10 kHz to 1 MHz. ADM7155ARD 2.3 V to 5.5 V 600 mA Adj 8-Lead SOIC 1 Adj means adjustable. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. Tel: 781.329.4700 20142016 Analog Devices, Inc. All rights reserved. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com NOISE SPECTRAL DENSITY (nV/Hz) 12324-001 12324-046ADM7154 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Applications Information .............................................................. 15 Applications ....................................................................................... 1 ADIsimPower Design Tool ....................................................... 15 Typical Application Circuit ............................................................. 1 Capacitor Selection .................................................................... 15 General Description ......................................................................... 1 Undervoltage Lockout (UVLO) ............................................... 16 Revision History ............................................................................... 2 Programmable Precision Enable .............................................. 17 Specifications ..................................................................................... 3 Start-Up Time ............................................................................. 17 Absolute Maximum Ratings ............................................................ 5 REF, BYP, and VREG Pins......................................................... 18 Thermal Data ................................................................................ 5 Current-Limit and Thermal Overload Protection ................. 18 Thermal Resistance ...................................................................... 5 Thermal Considerations ............................................................ 18 ESD Caution .................................................................................. 5 PCB Layout Considerations .......................................................... 21 Pin Configurations and Function Descriptions ........................... 6 Outline Dimensions ....................................................................... 22 Typical Performance Characteristics ............................................. 7 Ordering Guide .......................................................................... 23 Theory of Operation ...................................................................... 14 REVISION HISTORY 8/2016Rev. A to Rev. B Changes to Programmable Precision Enable Section and Figure 52 .......................................................................................... 17 12/2014Rev. 0 to Rev. A Changes to Figure 35 to Figure 40 ................................................ 12 Changes to Figure 44 ...................................................................... 15 10/2014Revision 0: Initial Version Rev. B Page 2 of 23