600 mA, Ultralow Noise, High PSRR, RF Linear Regulator Data Sheet ADM7155 FEATURES TYPICAL APPLICATION CIRCUIT Input voltage range: 2.3 V to 5.5 V ADM7155 V = 3.5V V = 3.0V IN OUT Output voltage range: 1.2 V to 3.4 V VIN VOUT C C IN OUT Maximum load current: 600 mA 10F 10F ON Low noise REF = 1.2V EN REF C 0.9 V rms total integrated noise from 100 Hz to 100 kHz REF OFF 1F R1 1.6 V rms total integrated noise from 10 Hz to 100 kHz V BYP Noise spectral density: 1.5 nV/Hz from 10 kHz to 1 MHz BYP REF SENSE V = 1.2V (R1 + R2)/R2 OUT C BYP PSRR: >90 dB from 200 Hz to 200 kHz 57 dB at 1 MHz 1F R2 Dropout voltage: 120 mV typical at V = 3.3 V, I = 600 mA OUT OUT V REG 1k < R2 < 200k VREG Initial accuracy: 0.5% C REG GND 10F Accuracy over line, load, and temperature: 2.0% (minimum), +1.5% (maximum) Figure 1. Regulated 3.0 V Output from 3.5 V Input Quiescent current, I = 4 mA at no load GND 10k Low shutdown current: 0.2 A NOISE FLOOR 1.0F Stable with a 10 F ceramic output capacitor 3.3F 8-lead LFCSP and 8-lead SOIC packages 1k 10F 33F Precision enable 100F 330F Supported by ADIsimPower tool 100 1000F APPLICATIONS Regulation to noise sensitive applications: PLLs, VCOs, and 10 PLLs with integrated VCOs Communications and infrastructure 1 Backhaul and microwave links 0.1 0.1 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 2. Noise Spectral Density for Different Values of CBYP GENERAL DESCRIPTION The ADM7155 is an adjustable linear regulator that operates The ADM7155 is available in 8-lead, 3 mm 3 mm LFCSP and from 2.3 V to 5.5 V and provides up to 600 mA of load current. 8-lead SOIC packages, making it not only a very compact Output voltages from 1.2 V to 3.4 V are possible depending on solution but also providing excellent thermal performance for the model. Using an advanced proprietary architecture, it applications requiring up to 600 mA of load current in a small, low profile footprint. provides high power supply rejection and ultralow noise, achieving excellent line and load transient response with only a Table 1. Related Devices 10 F ceramic output capacitor. Input Output 1 The ADM7155 is available in four models that optimize power Model Voltage Current Fixed/Adj Package dissipation and PSRR performance as a function of input and ADM7150ACP 4.5 V to 16 V 800 mA Fixed 8-Lead LFCSP output voltage. See Table 9 and Table 10 for selection guides. ADM7150ARD 4.5 V to 16 V 800 mA Fixed 8-Lead SOIC ADM7151ACP 4.5 V to 16 V 800 mA Adj 8-Lead LFCSP The ADM7155 regulator typical output noise is 0.9 V rms from ADM7151ARD 4.5 V to 16 V 800 mA Adj 8-Lead SOIC 100 Hz to 100 kHz for fixed output voltage options and 1.5 nV/Hz ADM7154ACP 2.3 V to 5.5 V 600 mA Fixed 8-Lead LFCSP for noise spectral density from 10 kHz to 1 MHz. ADM7154ARD 2.3 V to 5.5 V 600 mA Fixed 8-Lead SOIC 1 Adj means adjustable. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20142016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. NOISE SPECTRAL DENSITY (nV/ Hz) 12325-001 12325-002ADM7155 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Applications Information .............................................................. 15 Applications ....................................................................................... 1 ADIsimPower Design Tool ....................................................... 15 General Description ......................................................................... 1 Capacitor Selection .................................................................... 15 Typical Application Circuit ............................................................. 1 Undervoltage Lockout (UVLO) ............................................... 16 Revision History ............................................................................... 2 Programmable Precision Enable .............................................. 17 Specif icat ions ..................................................................................... 3 Start-Up Time ............................................................................. 17 Absolute Maximum Ratings ............................................................ 5 REF, BYP, and VREG Pins ......................................................... 18 Thermal Data ................................................................................ 5 Current-Limit and Thermal Overload Protection ................. 18 Thermal Resistance ...................................................................... 5 Thermal Considerations ............................................................ 18 ESD Caution .................................................................................. 5 Printed Circuit Board Layout Considerations ............................ 22 Pin Configurations and Function Descriptions ........................... 6 Outline Dimensions ....................................................................... 23 Typical Performance Characteristics ............................................. 7 Ordering Guide .......................................................................... 24 Theory of Operation ...................................................................... 14 REVISION HISTORY 8/2016Rev. B to Rev. C Changes to Programmable Precision Enable Section and Figure 53 .......................................................................................... 17 9/2015Rev. A to Rev. B Changed 3.0 V to 2.4 V .................................................................. 14 12/2014Rev. 0 to Rev. A Changes to Figure 35 to Figure 40 ................................................ 12 Changes to Figure 45 ...................................................................... 15 10/2014Revision 0: Initial Version Rev. C Page 2 of 24