Single-Chip, DSP-Based a High Performance Motor Controller ADMC401 Internal or External Voltage Reference FEATURES Out-of-Range Detection 26 MIPS Fixed-Point DSP Core Voltage Reference Single Cycle Instruction Execution (38.5 ns) Internal 2.0 V 2.0% Voltage Reference ADSP-21xx Family Code Compatible Three-Phase 16-Bit PWM Generation Unit 16-Bit Arithmetic and Logic Unit (ALU) Programmable Switching Frequency, Dead Time and Single Cycle 16-Bit 16-Bit Multiply and Accumulate Minimum Pulsewidth Into 40-Bit Accumulator (MAC) Edge Resolution of 38.5 ns 32-Bit Shifter (Logical and Arithmetic) One or Two Updates per Switching Period Multifunction Instructions Hardware Polarity Control Single Cycle Context Switch Individual Enable/Disable of Each Output Zero Overhead Looping High Frequency Chopping Mode Conditional Instruction Execution Dedicated Shutdown Pin (PWMTRIP) Two Independent Data Address Generators Additional Shutdown Pins in I/O System Memory Configuration High Output Sink and Source Capability (10 mA) 2K 24-Bit Internal Program Memory RAM Incremental Encoder Interface Unit 2K 24-Bit Internal Program Memory ROM Quadrature Rates to 17.3 MHz 1K 16-Bit Internal Data Memory RAM Programmable Filtering of Encoder Inputs 14-Bit Address Bus and 24-Bit Data Bus for External Alternative Frequency and Direction Mode Memory Expansion Two Registration Inputs to Latch Count Value High Resolution Multichannel ADC Optional Hardware Reset of Counter 12-Bit Pipeline Flash Analog-to-Digital Converter Single North Marker Mode Eight Dedicated Analog Inputs Count Error Monitor Function Simultaneous Sampling Capability Dedicated 16-Bit Loop Timer (Periodic Interrupts) All Eight Inputs Converted in <2 s Companion Encoder Event (1/T) Timer 4.0 V p-p Input Voltage Range PWM Synchronized or External Convert Start (Continued on Page 14) FUNCTIONAL BLOCK DIAGRAM 26 MIPS DSP CORE PM ROM MEMORY MOTOR CONTROL 2K 24 PERIPHERALS DATA ADDRESS PM DM WATCH- POWER- EVENT DIGITAL GENERATORS INTERRUPT ENCODER PROGRAM DOG ON RAM RAM CAPTURE I/O CONTROLLER INTERFACE SEQUENCER 2K 24 1K 16 TIMER RESET UNIT UNIT DAG 1 DAG 2 PROGRAM MEMORY ADDRESS EXTERNAL ADDRESS BUS DATA MEMORY ADDRESS PROGRAM MEMORY DATA EXTERNAL DATA BUS DATA MEMORY DATA SERIAL PORTS PRECISION 16-BIT 2 CHANNEL ARITHMETIC UNITS INTERVAL 8 CHANNEL VOLTAGE PWM AUXILIARY SPORT 0 SPORT 1 TIMER 12-BIT ADC REFERENCE GENERATION ALU SHIFTER PWM MAC REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties Tel: 781/329-4700 World Wide Web Site: ADMC401SPECIFICATIONS (V = AV = 5 V 5%, GND = AGND = 0 V, T = 40 C to +85 C, DD DD AMB RECOMMENDED OPERATING CONDITIONS CLKIN = 13 MHz, unless otherwise noted) B Grade Parameter Min Max Unit V Digital Supply Voltage 4.75 5.25 V DD AV Analog Supply Voltage 4.75 5.25 V DD T Ambient Operating Temperature 40 +85 C AMB ELECTRICAL CHARACTERISTICS Parameter Test Conditions Min Max Unit 1, 2, 3 V HI-Level Input Voltage V = max 2.0 V IH DD 1, 2, 3 V LO-Level Input Voltage V = min 0.8 V IL DD 1, 3, 4, 5, 6 V HI-Level Output Voltage V = min, I = 1.0 mA 2.4 V OH DD OH V = min, I = 0.1 mA V 0.3 V DD OH DD 1, 3, 4, 5, 6 V LO-Level Output Voltage V = min, I = 2.0 mA 0.4 V OL DD OL 5 V HI-Level Output Voltage V = min, I = 10.0 mA 2.4 V OH DD OH 5 V LO-Level Output Voltage V = min, I = 10.0 mA 1.2 V OL DD OL 7 I HI-Level Input Current V = max, V = V max 10 A IH DD IN DD 8 I HI-Level Input Current V = max, V = V max 100 A IH DD IN DD 9 I HI-Level Input Current V = max, V = V max 10 A IH DD IN DD 7 I LO-Level Input Current V = max, V = 0 V 10 A IL DD IN 8 I LO-Level Input Current V = max, V = 0 V 10 A IL DD IN 9 I LO-Level Input Current V = max, V = 0 V 100 A IL DD IN 10 I HI-Level Three-State Leakage Current V = max, V = V max 10 A OZH DD IN DD 10 I LO-Level Three-State Leakage Current V = max, V = 0 V 10 A OZL DD IN 11 I Digital Supply Current (Idle) V = max 40 mA DD DD 12 I Digital Supply Current (Dynamic) V = max 110 mA DD DD I Analog Supply Current AV = max 60 mA DD DD 13 C Input Pin Capacitance V = 2.5 V, f = 1 MHz, 8 pF I IN IN T = +25C AMB 13, 14 C Output Pin Capacitance V = 2.5 V, f = 1 MHz, 8 pF O IN IN T = +25C AMB NOTES 1 Bidirectional pins: D0D23, RFS0, RFS1, TFS0, TFS1, SCLK0 and SCLK1, PIO0PIO11. 2 Input only pins: PWMTRIP, PWMPOL, PWMSR, RESET, EIA, EIB, EIZ, EIS, ETU0, ETU1, DR1A, DR1B, DR0, CLKIN, CONVST, MMAP, BMODE, BR and PWD. 3 Programmable I/O Pins (PIO0PIO11). 4 Output pins: PWMSYNC, AUX0, AUX1, CLKOUT, DT0, DT1, BG, BGH, PMS, DMS, BMS, RD, WR, PWDACK and A0A13. 5 Output pins: AH, AL, BH, BL, CH and CL. 6 Although specified for TTL outputs, all ADMC401 outputs are CMOS-compatible and will drive to V 0.3 V and GND+0.3 V assuming no dc loads. DD 7 Input only pins RESET, EIA, EIB, EIZ, EIS, ETU0, ETU1, DR1A, DR1B, DR0, CLKIN, CONVST, MMAP, BMODE, BR and PWD. 8 Input pins with internal pull-down PIO0PIO11 and PWMTRIP. 9 Input pins with internal pull-up, PWMPOL and PWMSR. 10 Three-statable pins: A0A13, D0D23, PMS, DMS, BMS, RD, WR, DT0, DT1, RFS0, RFS1, TFS0, TFS1, SCLK0, SCLK1. 11 Idle refers execution of the IDLE instruction. Deasserted pins are driven to V or GND. Current reflects device operation with CLKOUT disabled. DD 12 Current reflects device operating with no output loads. 13 Guaranteed but not tested. 14 Output Pin Capacitance is the capacitive load for any three-state output pin. Specifications subject to change without notice. REV. B 2