Dual-Mode, Ka Band Upconverter with Integrated Fractional-N PLL and VCO Data Sheet ADMV4530 FEATURES GENERAL DESCRIPTION RF output frequency range: 27 GHz to 31 GHz The ADMV4530 is a highly integrated upconverter with an Two upconversion modes inphase/quadrature (I/Q) mixer that is ideally suited for next Direct upconversion from differential baseband I/Q (I/Q mode) generation Ka band satellite communications. Single upper sideband upconversion (IF mode) An integrated low phase noise, fractional-N phase-locked loop 1 dB bandwidth: 500 MHz (I/Q mode) (PLL) with a voltage controlled oscillator (VCO) and internal Input frequency range: 2 GHz to 3 GHz (IF mode) 2 multiplier generate the necessary on-chip local oscillator Matched, 50 , single-ended RF output (LO) signal for the I/Q mixer, eliminating the need for external Matched, 50 , single-ended IF input frequency synthesis. The VCO uses an internal autocalibration Programmable baseband I/Q common mode-voltage routine that allows the PLL to select the necessary settings and Sideband rejection and carrier feedthrough optimization locks in approximately 100 s. Combined RF and IF gain dynamic range: 70 dB The single-ended reference input to the PLL operates up to Programmable automatic IF gain control 500 MHz and features internal reference dividers and a multiplier Programmable via 3-wire or 4-wire SPI for added flexibility. Additionally, the phase frequency detector 40-terminal, 6 mm 6 mm, RoHS compliant LGA (PFD) comparison frequency can be up to 250 MHz for integer mode and 160 MHz for fraction-N mode. APPLICATIONS The upconverter consists of an I/Q mixer that can operate in Satellite communication either I/Q mode with 500 MHz of bandwidth or in IF mode up Point to point microwave communication to 3 GHz of bandwidth, which allows various radio architectures and backward compatibility with legacy systems. Immediately following the I/Q mixer are stages of gain and variable attenuation. The configuration can achieve a minimum 1 dB compression point (P1dB) compression point of 19 dBm, eliminating the need for external stages of gain. A programmable 4-wire serial port interface (SPI) allows adjustment of the quadrature phase for optimum sideband suppression. In addition, the SPI allows nulling of LO feedthrough in IF mode. In I/Q mode, the LO feedthrough can be nulled by applying external dc offset to the differential baseband I/Q inputs. An IF automatic gain control (AGC) adjusts the IF variable gain amplifier (VGA) to compensate for input power variations. During normal operation, this AGC feature can be enabled or disabled via the SPI. When disabled during normal operation, the AGC feature only works on a test tone during power-down mode to track temperature variations. The ADMV4530 upconverter comes in a RoHs compliant, 6 mm 6 mm, 40-terminal land grid array (LGA) package. The ADMV4530 operates over the 40C to +85C case temperature range. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. Tel: 781.329.4700 2020 Analog Devices, Inc. All rights reserved. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com ADMV4530 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Charge Pump Current Setup .................................................... 30 Applications ...................................................................................... 1 Bleed Current (CP BLEED) Setup .......................................... 30 General Description ......................................................................... 1 MUXOUT ................................................................................... 31 Revision History ............................................................................... 2 Digital Lock Detect .................................................................... 31 Functional Block Diagram .............................................................. 3 VCO Autocalibration ................................................................ 31 Specifications .................................................................................... 4 VCO Calibration Data Read Back ........................................... 31 I/Q Mode ....................................................................................... 5 VCO Calibration Data Manual Writing ................................. 31 IF Mode.......................................................................................... 6 Autocalibration Lock Time....................................................... 32 Absolute Maximum Ratings ........................................................... 7 Synthesizer Lock Timeout ........................................................ 32 Thermal Resistance ...................................................................... 7 VCO Band Selection Time ........................................................ 32 ESD Caution.................................................................................. 7 PLL Settling Time ....................................................................... 32 Pin Configuration and Function Descriptions ............................ 8 Chip Temperature Read Back .................................................. 32 Typical Performance Characteristics ........................................... 10 RF Output Driver ....................................................................... 33 I/Q Mode ..................................................................................... 10 I/Q Mode Mixer Setup .............................................................. 33 IF Mode........................................................................................ 15 I/Q Mode LO Nulling ................................................................ 33 Return Loss and Leakages ......................................................... 20 I/Q Mode Sideband Rejection Nulling ................................... 33 VCO and PLL.............................................................................. 22 IF Gain Control .......................................................................... 33 Upconverter M N Spurious Performance ........................... 26 IF Mode Mixer Setup ................................................................. 33 Theory of Operation ...................................................................... 27 IF Mode LO Nulling .................................................................. 34 SPI Configuration ...................................................................... 27 IF Mode Sideband Rejection Nulling ...................................... 34 Register Map Sections ................................................................ 27 Applications Information ............................................................. 35 Double Buffered Registers ......................................................... 27 IF AGC Configuration .............................................................. 35 Start-Up Initialization Sequence .............................................. 27 Error Vector Magnitude Performance .................................... 35 Frequency Update Sequence ..................................................... 28 PLL Lock Time in IF and I/Q Mode ........................................ 36 Reference Input .......................................................................... 28 Power Up and Down ................................................................. 36 N Counter .................................................................................... 28 Register Summary .......................................................................... 37 INT, FRAC, MOD, and R Counter Relationship .................. 28 Register Details ............................................................................... 39 INT N Mode ................................................................................ 29 Outline Dimensions ....................................................................... 59 Phase Frequency Detector and Charge Pump ........................... 29 Ordering Guide .......................................................................... 59 Loop Filter ................................................................................... 29 REVISION HISTORY 3/2020Rev. 0 to Rev. A Change to Data Sheet Title .............................................................. 1 3/2020Revision 0: Initial Version Rev. A Page 2 of 59