E-Band Low Noise Downconverter SiP, 71 GHz to 76 GHz Data Sheet ADMV7410 FEATURES FUNCTIONAL BLOCK DIAGRAM Conversion gain: 13 dB typical Image rejection: 30 dBc typical Noise figure: 5 dB typical Input IP3: 1 dBm typical 34 33 32 31 30 29 28 27 26 25 24 23 Input IP2: 28 dBm typical Input P1dB: 8 dBm typical 6 LO leakage at RFIN: <55 dBm typical I/Q amplitude imbalance: 0.2 dB typical GND 1 I/Q phase imbalance: 5 typical IF IP 2 Fully integrated, surface-mount, 34-terminal, 11 mm x6 IF IN 3 13 mm LGA CAV package IF QN 4 APPLICATIONS IF QP 5 E-band communication systems GND High capacity wireless backhauls 6 PORT 1 RFIN Test and measurement GND 7 LNA Aerospace and defense GND 8 GND 9 ADMV7410 GND 10 11 12 13 14 15 16 17 18 19 20 21 22 Figure 1. GENERAL DESCRIPTION The ADMV7410 is a fully integrated system in package (SiP) outputs are provided for direct conversion applications. in phase/quadrature (I/Q) downconverter that operates Alternatively, the outputs can be combined using an external between an intermediate frequency (IF) output range of dc and 90 hybrid and two external 180 hybrids for single-ended 2 GHz and a RF input range of 71 GHz and 76 GHz. The device applications. provides a small signal conversion gain of 13 dB with 30 dBc of The ADMV7410 comes in a fully integrated, surface-mount, image rejection. The ADMV7410 uses a low noise amplifier 34-terminal, 11 mm 13 mm, chip array small outline no lead followed by an image rejection mixer that is driven by a 6 cavity (LGA CAV) package. The ADMV7410 operates over the local oscillator (LO) multiplier. Differential I and Q mixer 40C to +85C case temperature range. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. Tel: 781.329.4700 2019-2021 Analog Devices, Inc. All rights reserved. No license is granted by implication or otherwise under any patent or patent rights of Analog Technical Support www.analog.com Devices. Trademarks and registered trademarks are the property of their respective owners. GND GND GND VG MIXER VD AMP VD34 LNA GND GND VG34 LNA VG AMP GND GND GND VD MULT VD12 LNA GND VG MULT GND GND VG12 LNA LOIN GND GND GND 20966-001ADMV7410 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Return Loss and 6 LO Leakage .............................................. 19 Applications ...................................................................................... 1 Spurious Performance ............................................................... 20 Functional Block Diagram .............................................................. 1 Theory of Operation ...................................................................... 21 General Description ......................................................................... 1 Applications Information ............................................................. 22 Revision History ............................................................................... 2 Power-Up Bias Sequence .......................................................... 22 Specifications .................................................................................... 3 Power-Down Sequence ............................................................. 22 Absolute Maximum Ratings ........................................................... 4 Layout .......................................................................................... 22 Thermal Resistance ...................................................................... 4 Typical Application Circuit .......................................................... 24 ESD Caution.................................................................................. 4 Outline Dimensions ....................................................................... 25 Pin Configuration and Function Descriptions ............................ 5 Ordering Guide .......................................................................... 25 Interface Schematics .................................................................... 6 Typical Performance Characteristics ............................................. 7 REVISION HISTORY 10/2021Rev. A to Rev. B Updated Outline Dimensions ....................................................... 25 7/2019Revision A: Initial Version Rev. B Page 2 of 25