622 Mbps Clock and Data Recovery IC Data Sheet ADN2806 FEATURES GENERAL DESCRIPTION Exceeds SONET requirements for jitter transfer/ The ADN2806 provides the receiver functions for clock and generation/tolerance data recovery, and data retiming for 622 Mbps NRZ data. The Patented clock recovery architecture ADN2806 automatically locks to 622 Mbps data without the No reference clock required need for an external reference clock or programming. All Loss-of-lock indicator SONET jitter requirements are met, including jitter transfer, 2 I C interface to access optional features jitter generation, and jitter tolerance. All specifications are Single-supply operation: 3.3 V quoted for 40C to +85C ambient temperature, unless Low power: 359 mW typical otherwise noted. 5 mm 5 mm, 32-lead LFCSP, Pb free This device, together with a PIN diode, TIA preamplifier, and a APPLICATIONS lim amp can implement a highly integrated, low cost, low power BPON ONT fiber optic receiver. SONET OC-12 The ADN2806 is available in a compact 5 mm 5 mm, WDM transponders 32-lead LFCSP. Regenerators/repeaters Test equipment Broadband cross-connects and routers FUNCTIONAL BLOCK DIAGRAM REFCLKP/REFCLKN LOL CF1 CF2 VCC VEE (OPTIONAL) LOOP FREQUENCY FILTER DETECT PIN PHASE PHASE LOOP BUFFER VCO NIN SHIFTER DETECT FILTER VREF DATA RE-TIMING 2 2 ADN2806 DATAOUTP/ CLKOUTP/ DATAOUTN CLKOUTN Figure 1. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 20062012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 05831-001ADN2806 TABLE OF CONTENTS Features .............................................................................................. 1 Jitter Specifications......................................................................... 10 Applications....................................................................................... 1 Theory of Operation ...................................................................... 11 General Description ......................................................................... 1 Functional Description.................................................................. 13 Functional Block Diagram .............................................................. 1 Frequency Acquisition............................................................... 13 Revision History ............................................................................... 2 Input Buffer Amplifier............................................................... 13 Specifications..................................................................................... 3 Lock Detector Operation .......................................................... 13 Jitter Specifications....................................................................... 3 SQUELCH Modes...................................................................... 13 2 Output and Timing Specifications ............................................. 4 I C Interface ................................................................................ 14 Absolute Maximum Ratings............................................................ 5 Reference Clock (Optional) ...................................................... 15 Thermal Characteristics .............................................................. 5 Applications Information .............................................................. 17 ESD Caution.................................................................................. 5 PCB Design Guidelines ............................................................. 17 Timing Characteristics..................................................................... 6 Outline Dimensions....................................................................... 20 Pin Configuration and Function Descriptions............................. 7 Ordering Guide .......................................................................... 20 2 I C Interface Timing and Internal Register Description............. 8 REVISION HISTORY 4/12Rev. B to Rev. C 5/10Rev. A to Rev. B Change to General Description Section ........................................ 1 Changes to Figure 5 and Table 5......................................................7 Change to Output Clock Range Parameter, Table 1 .................... 3 Changes to Figure 19...................................................................... 17 Changed Pin 1 from VCC to TEST1 and Pin 32 from VCC 2/09Rev. 0 to Rev. A to TEST2 Throughout Changes to Figure 5 and Table 5............ 7 Updated Outline Dimensions....................................................... 20 Changes to Table 6 and Table 10..................................................... 9 Changes to Ordering Guide .......................................................... 20 Changes to Ordering Guide Updated Outline Dimensions .... 20 2/06Revision 0: Initial Version Rev. C Page 2 of 20