155/622 Mb/s Clock and Data Recovery IC with Integrated Limiting Amplifier Data Sheet ADN2807 FEATURES GENERAL DESCRIPTION Meets SONET requirements for jitter transfer/ The ADN2807 provides the receiver functions of quantization, generation/tolerance signal level detect, and clock and data recovery at rates of OC-3, Quantizer sensitivity: 4 mV typical OC-12, and 15/14 FEC. All SONET jitter requirements are met, Adjustable slice level: 100 mV including jitter transfer, jitter generation, and jitter tolerance. Patented clock recovery architecture All specifications are quoted for 40C to +85C ambient Loss-of-signal detect range: 3 mV to 15 mV temperature, unless otherwise noted. Single-reference clock frequency for all rates, including The device is intended for WDM system applications and can 15/14 (7%) wrapper rate be used with either an external reference clock or an on-chip Choice of 19.44 MHz, 38.88 MHz, 77.76 MHz, or oscillator with external crystal. Both native rates and 15/14 rate 155.52 MHz REFCLK digital wrappers are supported by the ADN2807, without any REFCLK inputs: LVPECL/LVDS/LVCMOS/LVTTL compatible change of reference clock. (LVPECL/LVDS only at 155.52 MHz) This device, together with a PIN diode and a TIA preamplifier, Optional 19.44 MHz on-chip oscillator to be used with can implement a highly integrated, low cost, low power, fiber external crystal optic receiver. Loss-of-lock indicator Loopback mode for high speed test data The receiver front end signal detect circuit indicates when the Output squelch and bypass features input signal level has fallen below a user adjustable threshold. Single-supply operation: 3.3 V The signal detect circuit has hysteresis to prevent chatter at the Low power: 540 mW typical output. 7 mm 7 mm, 48-lead LFCSP The ADN2807 is available in a compact 7 mm 7 mm 48-lead APPLICATIONS chip-scale package (LFCSP). SONET OC-3/-12, SDH STM-1/-4 and, 15/14 FEC rates WDM transponders Regenerators/repeaters Test equipment Passive optical networks FUNCTIONAL BLOCK DIAGRAM SLICEP/N VCC VEE LOL CF1 CF2 ADN2807 2 LOOP 2 FILTER REFSEL 0..1 PIN 2 /n REFCLKP/N FREQUENCY PHASE LOOP PHASE XO1 QUANTIZER VCO LOCK SHIFTER FILTER DET. DETECTOR NIN XTAL OSC XO2 FRACTIONAL DIVIDER VREF REFSEL LEVEL DATA DIVIDER DETECT RETIMING 1/2/4/16 3 2 2 THRADJ SDOUT DATAOUTP/N CLKOUTP/N SEL 0..2 Figure 1. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20042016 Analog Devices, Inc. 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Technical Support www.analog.com 03877-0-001ADN2807 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 11 Applications ....................................................................................... 1 Functional Description .................................................................. 13 General Description ......................................................................... 1 Multirate Clock and Data Recovery ........................................ 13 Functional Block Diagram .............................................................. 1 Limiting Amplifier ..................................................................... 13 Table of Contents .............................................................................. 2 Slice Adjust .................................................................................. 13 Revision History ............................................................................... 2 Loss-of-Signal (LOS) Detector ................................................. 13 Specifications ..................................................................................... 3 Reference Clock .......................................................................... 13 Absolute Maximum Ratings ............................................................ 5 Lock Detector Operation .......................................................... 14 Thermal Characteristics .............................................................. 5 Squelch Mode ............................................................................. 15 ESD Caution .................................................................................. 5 Test ModesBypass and Loop-back ....................................... 15 Pin Configuration and Function Descriptions ............................. 6 Application Information ................................................................ 16 Definition of Terms .......................................................................... 9 PCB Design Guidelines ............................................................. 16 Maximum, Minimum, and Typical Specifications................... 9 Choosing AC Coupling Capacitors ......................................... 18 Input Sensitivity and Input Overdrive ....................................... 9 DC-Coupled Application .......................................................... 18 Single-Ended vs. Differential ...................................................... 9 LOL Toggling during Loss of Input Data ................................ 18 LOS Response Time ................................................................... 10 Outline Dimensions ....................................................................... 20 Jitter Specifications ..................................................................... 10 Ordering Guide .......................................................................... 20 REVISION HISTORY 5/16Rev. A to Rev. B Changes to Figure 2 and Table 3 ..................................................... 6 Changes to Figure 20 ...................................................................... 17 Updated Outline Dimensions ....................................................... 19 Changes to Ordering Guide .......................................................... 19 5/04Rev. 0 to Rev. A Changes to Specifications ................................................................ 3 Change to Table 7 and Table 8 ...................................................... 13 1/04Revision 0: Initial Version Rev. B Page 2 of 21