OC-48/OC-48 FEC Clock and Data Recovery Data Sheet ADN2811 FEATURES PRODUCT DESCRIPTION Meets SONET requirements for jitter transfer/generation/ The ADN2811 provides the receiver functions of quantization, tolerance signal level detect, and clock and data recovery at OC-48 and Quantizer sensitivity: 4 mV typical OC-48 FEC rates. All SONET jitter requirements are met, Adjustable slice level: 100 mV including jitter transfer, jitter generation, and jitter tolerance. 1.9 GHz minimum bandwidth All specifications are quoted for 40C to +85C ambient Patented clock recovery architecture temperature, unless otherwise noted. Loss of signal detect range: 3 mV to 15 mV The device is intended for WDM system applications and can Single reference clock frequency for both native SONET and be used with either an external reference clock or an on-chip 15/14 (7%) wrapper rate oscillator with external crystal. Both the 2.48 Gbps and 2.66 Gbps Choice of 19.44 MHz, 38.88 MHz, 77.76 MHz, or 155.52 MHz digital wrapper rates are supported by the ADN2811, without REFCLK any change of reference clock. LVPECL/LVDS/LVCMOS/LVTTL compatible inputs This device, together with a PIN diode and a TIA preamplifier, (LVPECL/LVDS only at 155.52 MHz) can implement a highly integrated, low cost, low power, fiber 19.44 MHz on-chip oscillator to be used with external crystal optic receiver. Loss of lock indicator Loopback mode for high speed test data The receiver front end signal detect circuit indicates when the Output squelch and bypass features input signal level has fallen below a user-adjustable threshold. Single-supply operation: 3.3 V The signal detect circuit has hysteresis to prevent chatter at the Low power: 540 mW typical output. 7 mm 7 mm, 48-lead LFCSP The ADN2811 is available in a compact, 7 mm 7 mm, 48-lead APPLICATIONS chip scale package. SONET OC-48, SDH STM-16, and 15/14 FEC WDM transponders Regenerators/repeaters Test equipment Backplane applications FUNCTIONAL BLOCK DIAGRAM SLICEP/N VCC VEE LOL CF1 CF2 ADN2811 2 LOOP 2 FILTER REFSEL 0..1 PIN 2 /n REFCLKP/N FREQUENCY PHASE LOOP PHASE QUANTIZER LOCK XO1 VCO SHIFTER DET. FILTER DETECTOR NIN XTAL OSC XO2 FRACTIONAL DIVIDER VREF LEVEL DATA REFSEL DETECT RETIMING 2 2 THRADJ SDOUT DATAOUTP/N CLKOUTP/N RATE Figure 1. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20022016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 03019-B-001ADN2811 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Functional Description .................................................................. 12 Applications ....................................................................................... 1 Clock and Data Recovery .......................................................... 12 Product Description ......................................................................... 1 Limiting Amplifier ..................................................................... 12 Functional Block Diagram .............................................................. 1 Slice Adjust .................................................................................. 12 Revision History ............................................................................... 2 Loss of Signal (LOS) Detector .................................................. 12 Specifications ..................................................................................... 3 Reference Clock .......................................................................... 12 Absolute Maximum Ratings ............................................................ 5 Lock Detector Operation .......................................................... 13 Thermal Characteristics .............................................................. 5 Squelch Mode ............................................................................. 14 ESD Caution .................................................................................. 5 Test Modes: Bypass and Loopback ........................................... 14 Pin Configuration and Functional Descriptions .......................... 6 Applications Information .............................................................. 15 Definition of Terms .......................................................................... 8 PCB Design Guidelines ............................................................. 15 Maximum, Minimum, and Typical Specifications................... 8 Choosing AC-Coupling Capacitors ......................................... 17 Input Sensitivity and Input Overdrive ....................................... 8 DC-Coupled Application .......................................................... 18 Single-Ended vs. Differential ...................................................... 8 LOL Toggling during Loss of Input Data ................................ 18 LOS Response Time ..................................................................... 9 Outline Dimensions ....................................................................... 19 Jitter Specifications ....................................................................... 9 Ordering Guide .......................................................................... 19 Theory of Operation ...................................................................... 10 REVISION HISTORY 5/16Rev. B to Rev. C Changes to Figure 2 and Table 3 ..................................................... 6 Changes to Figure 19 ...................................................................... 16 Updated Outline Dimensions ....................................................... 19 Changes to Ordering Guide .......................................................... 19 5/04Rev. A to Rev. B Updated Format .................................................................. Universal Changes to Table 6 and Table 7 ..................................................... 13 Updated Outline Dimensions ....................................................... 19 Changes to Ordering Guide .......................................................... 19 12/02Rev. 0 to Rev. A. Change to Functional Description Reference Clock ................. 10 Updated Outline Dimensions ....................................................... 16 Rev. C Page 2 of 20