Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp Data Sheet ADN2812 FEATURES GENERAL DESCRIPTION Serial data input: 12.3 Mb/s to 2.7 Gb/s The ADN2812 provides the receiver functions of quantization, Exceeds SONET requirements for jitter transfer/ signal level detect, and clock and data recovery for continuous generation/tolerance data rates from 12.3 Mb/s to 2.7 Gb/s. The ADN2812 auto- Quantizer sensitivity: 6 mV typical matically locks to all data rates without the need for an external Adjustable slice level: 100 mV reference clock or programming. All SONET jitter requirements Patented clock recovery architecture are met, including jitter transfer, jitter generation, and jitter Loss of signal (LOS) detect range: 3 mV to 15 mV tolerance. All specifications are quoted for 40C to +85C Independent slice level adjust and LOS detector ambient temperature, unless otherwise noted. No reference clock required This device, together with a PIN diode and a TIA preamplifier, Loss of lock indicator can implement a highly integrated, low cost, low power fiber 2 I C interface to access optional features optic receiver. Single-supply operation: 3.3 V The receiver front end, loss of signal (LOS) detector circuit Low power: 750 mW typical indicates when the input signal level has fallen below a user- 5 mm 5 mm 32-lead LFCSP adjustable threshold. The LOS detect circuit has hysteresis to APPLICATIONS prevent chatter at the output. SONET OC-1/OC-3/OC-12/OC-48 and all associated FEC rates The ADN2812 is available in a compact 5 mm 5 mm 32-lead Fibre Channel, 2 Fibre Channel, GbE, HDTV lead frame chip scale package (LFCSP). WDM transponders Regenerators/repeaters Test equipment Broadband cross-connects and routers FUNCTIONAL BLOCK DIAGRAM REFCLKP/N LOL CF1 CF2 VCC VEE (OPTIONAL) 2 LOOP FREQUENCY FILTER SLICEP/N DETECT PIN PHASE PHASE LOOP QUANTIZER VCO NIN SHIFTER DETECT FILTER VREF LOS DATA DETECT RE-TIMING 2 2 THRADJ LOS DATAOUTP/N CLKOUTP/N Figure 1. Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 20042012 Analog Devices, Inc. All rights reserved. 04228-001ADN2812 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Jitter Generation ......................................................................... 13 Applications ....................................................................................... 1 Jitter Transfer .............................................................................. 13 General Description ......................................................................... 1 Jitter Tolerance ............................................................................ 13 Functional Block Diagram .............................................................. 1 Theory of Operation ...................................................................... 14 Revision History ............................................................................... 2 Functional Description .................................................................. 16 Specifications ..................................................................................... 3 Frequency Acquisition ............................................................... 16 Jitter Specifications ....................................................................... 4 Limiting Amplifier ..................................................................... 16 Output and Timing Specifications ............................................. 5 Slice Adjust .................................................................................. 16 Absolute Maximum Ratings ............................................................ 6 LOS Detector .............................................................................. 16 Thermal Characteristics .............................................................. 6 Lock Detector Operation .......................................................... 16 ESD Caution .................................................................................. 6 Harmonic Detector .................................................................... 17 Timing Characteristics ..................................................................... 7 Squelch Mode ............................................................................. 17 2 Pin Configuration and Function Descriptions ............................. 8 I C Interface ................................................................................ 18 Typical Performance Characteristics ............................................. 9 Reference Clock (Optional) ...................................................... 18 2 I C Interface Timing and Internal Register Description ........... 10 Applications Information .............................................................. 21 Terminology .................................................................................... 12 PCB Design Guidelines ............................................................. 21 Input Sensitivity and Input Overdrive ..................................... 12 DC-Coupled Application .......................................................... 23 Single-Ended vs. Differential .................................................... 12 Coarse Data Rate Readback Look-Up Table ............................... 24 LOS Response Time ................................................................... 12 Outline Dimensions ....................................................................... 26 Jitter Specifications ......................................................................... 13 Ordering Guide .......................................................................... 26 REVISION HISTORY 3/12Rev. D to Rev. E Changes to LTR Mode Description ............................................. 19 Changes to Ordering Guide .......................................................... 26 Updated Outline Dimensions ....................................................... 26 Changes to Ordering Guide .......................................................... 26 11/04Rev. 0 to Rev. A 5/10Rev. C to Rev. D Change to Specification .................................................................... 3 Updated Outline Dimensions ....................................................... 26 Changes to Figure 4, Table 5 ........................................................... 8 Changes to Using the Reference Clock to Lock onto Data Changes to Figure 24 ...................................................................... 21 Section .............................................................................................. 19 2/09Rev. B to Rev. C 3/04Revision 0: Initial Version Updated Outline Dimensions ....................................................... 26 Changes to Ordering Guide .......................................................... 26 6/07Rev. A to Rev. B Changes to Table 1 ............................................................................ 3 Changes to Table 6 .......................................................................... 11 Rev. E Page 2 of 28