Continuous Rate 10 Mb/s to 675 Mb/s Clock and Data Recovery IC Data Sheet ADN2816 FEATURES GENERAL DESCRIPTION Serial data input: 10 Mb/s to 675 Mb/s The ADN2816 provides the receiver functions of quantization Exceeds SONET requirements for jitter transfer/ and clock and data recovery for continuous data rates from generation/tolerance 10 Mb/s to 675 Mb/s. The ADN2816 automatically locks to all Patented clock recovery architecture data rates without the need for an external reference clock or No reference clock required programming. All SONET jitter requirements are met, Loss-of-lock indicator including jitter transfer, jitter generation, and jitter tolerance. 2 I C interface to access optional features All specifications are quoted for 40C to +85C ambient Single-supply operation: 3.3 V temperature, unless otherwise noted. Low power: 366 mW typical The ADN2816 is available in a compact 5 mm 5 mm 32-lead 5 mm 5 mm 32-lead LFCSP, Pb free LFCSP. APPLICATIONS SONET OC-1/-3/-12 and all associated FEC rates Fibre Channel, ESCON, Fast Ethernet, SDI WDM transponders Regenerators/repeaters Test equipment Broadband crossconnects and routers FUNCTIONAL BLOCK DIAGRAM REFCLKP/REFCLKN LOL CF1 CF2 VCC VEE (OPTIONAL) LOOP FREQUENCY FILTER DETECT PIN PHASE PHASE LOOP BUFFER VCO NIN SHIFTER DETECT FILTER VREF DATA RE-TIMING 2 ADN2816 2 DATAOUTP/ CLKOUTP/ DRVCC DRVEE DVCC DVEE DATAOUTN CLKOUTN Figure 1. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 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All rights reserved. 04948-0-001ADN2816 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 12 Applications ....................................................................................... 1 Functional Description .................................................................. 14 General Description ......................................................................... 1 Frequency Acquisition ............................................................... 14 Functional Block Diagram .............................................................. 1 Input Buffer ................................................................................. 14 Revision History ............................................................................... 2 Lock Detector Operation .......................................................... 14 Specifications ..................................................................................... 3 Harmonic Detector .................................................................... 15 Jitter Specifications ....................................................................... 4 SQUELCH Mode ........................................................................ 15 2 Output and Timing Specifications ............................................. 5 I C Interface ................................................................................ 15 Absolute Maximum Ratings ............................................................ 6 Reference Clock (Optional) ...................................................... 16 Thermal Characteristics .............................................................. 6 Applications Information .............................................................. 19 ESD Caution .................................................................................. 6 PCB Design Guidelines ............................................................. 19 Timing Characteristics ..................................................................... 7 Coarse Data Rate Readback Look-Up Table ............................... 22 Pin Configuration and Function Descriptions ............................. 8 Outline Dimensions ....................................................................... 24 2 I C Interface Timing and Internal Register Description ............. 9 Ordering Guide .......................................................................... 24 Jitter Specifications ......................................................................... 11 REVISION HISTORY 2/12Rev. B to Rev. C Updated Outline Dimensions ........................................................ 24 Changes to Ordering Guide .......................................................... 24 5/10Rev. A to Rev. B Changes to Figure 5 and Table 5 ...................................................... 8 Changes to Figure 19 ....................................................................... 19 Added Exposed Pad Notation to Outline Dimensions .............. 24 2/09Rev. 0 to Rev. A Changes to Ordering Guide and Updated Outline Dimensions ................................................ 24 9/05Revision 0: Initial Version Rev. C Page 2 of 24