Continuous Rate 10 Mbps to 2.7 Gbps Clock and Data Recovery ICs Data Sheet ADN2817/ADN2818 FEATURES GENERAL DESCRIPTION Serial data input: 10 Mbps to 2.7 Gbps The ADN2817/ADN2818 provide the receiver functions of Exceeds ITU-T jitter specifications quantization, signal level detect, and clock and data recovery for Integrated limiting amplifier continuous data rates from 10 Mbps to 2.7 Gbps. The ADN2817/ 5 mV p-p sensitivity (ADN2817 only) ADN2818 automatically lock to all data rates without the need for Adjustable slice level: 100 mV (ADN2817 only) an external reference clock or programming. All SONET jitter Proprietary dual-loop clock recovery architecture requirements are exceeded, including jitter transfer, jitter generation, Programmable LOS detect (ADN2817 only) and jitter tolerance. All specifications are quoted for 40C to Integrated PRBS generator and detector +85C ambient temperature, unless otherwise noted. No reference clock required This device, together with a PIN diode and a TIA preamplifier, Loss of lock indicator can implement a highly integrated, low cost, and low power Supports double data rate fiber optic receiver. BERMON or sample phase adjust options The ADN2817/ADN2818 have many optional features available Rate selectivity without the use of a reference clock 2 2 through an I C interface. For example, the user can read back I C interface to access optional features the data rate onto which the ADN2817 or ADN2818 is locked, Single-supply operation: 3.3 V or the user can set the device to lock only to one particular data Low power rate if provisioning of data rates is required. A bit error rate 650 mW (ADN2817) monitor (BERMON) circuit provides an estimate of the received 600 mW (ADN2818) bit error rate (BER) without interruption of the data. 5 mm 5 mm 32-lead LFCSP Alternatively, the user can adjust the data sampling phase to APPLICATIONS optimize the received BER. SONET OC-1, OC-3, OC-12, OC-48, and all associated FEC rates The ADN2817/ADN2818 are available in a compact 5 mm Fibre Channel, 2 Fibre Channel, GbE, HDTV 5 mm, 32-lead, lead frame chip scale package. WDM transponders Regenerators/repeaters Test equipment FUNCTIONAL BLOCK DIAGRAM REFCLKP/REFCLKN (OPTIONAL) LOL VCC VEE CF1 CF2 ADN2817/ADN2818 SLICE FREQ/ LOOP SLICEP/ ADJUST LOCK FILTER SLICEN (ADN2817 DET ONLY) PIN LOOP PHASE PHASE VCO FILTER SHIFTER DET NIN VREF LOS DETECT DATA (ADN2817 RETIMING 2 I C ONLY) BERMON REGISTERS LOS DATAOUTP/ CLKOUTP/ VBER BERMODE SCK SDA THRADJ DATAOUTN CLKOUTN Figure 1. Rev. G Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20072019 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 06001-001ADN2817/ADN2818 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Jitter Tolerance ............................................................................ 19 Applications ....................................................................................... 1 Theory of Operation ...................................................................... 20 General Description ......................................................................... 1 Functional Description .................................................................. 22 Functional Block Diagram .............................................................. 1 Frequency Acquisition ............................................................... 22 Revision History ............................................................................... 3 Lock Detector Operation .......................................................... 22 Specifications ..................................................................................... 4 Harmonic Detector .................................................................... 23 Jitter Specifications ....................................................................... 5 Limiting Amplifier (ADN2817 Only) ..................................... 23 Output and Timing Specifications ............................................. 6 Slice Level Adjust (ADN2817 Only) ........................................ 23 Bit Error Rate Monitor Specifications ....................................... 8 Loss of Signal (LOS) Detector (ADN2817 Only)................... 23 Timing Characteristics ................................................................ 9 Sample Phase Adjust .................................................................. 24 Absolute Maximum Ratings .......................................................... 10 BER Monitor ............................................................................... 24 Thermal Characteristics ............................................................ 10 Squelch Mode ............................................................................. 25 2 ESD Caution ................................................................................ 10 I C Interface ................................................................................ 25 Pin Configuration and Function Descriptions ........................... 11 Reference Clock (Optional) ...................................................... 26 2 Typical Performance Characteristics ........................................... 12 Additional Features Available via the I C Interface ............... 28 2 I C-Interface Timing and Internal Register Description .......... 14 Applications Information .............................................................. 30 Terminology .................................................................................... 18 PCB Design Guidelines ............................................................. 30 Input Sensitivity and Input Overdrive ..................................... 18 DC-Coupled Application .......................................................... 32 Single-Ended vs. Differential .................................................... 18 Coarse Data Rate Readback Lookup Table ................................. 33 LOS Response Time ................................................................... 18 HI CODE and LO CODE Lookup Table .................................. 35 Jitter Specifications ......................................................................... 19 Outline Dimensions ....................................................................... 38 Jitter Generation ......................................................................... 19 Ordering Guide .......................................................................... 38 Jitter Transfer............................................................................... 19 Rev. G Page 2 of 38