Multirate to 2.7 Gbps Clock and Data Recovery IC with Integrated Limiting Amp Data Sheet ADN2819 FEATURES PRODUCT DESCRIPTION Meets SONET requirements for jitter The ADN2819 provides the receiver functions of quantization, transfer/generation/tolerance signal level detect, and clock and data recovery at rates of OC-3, Quantizer sensitivity: 4 mV typical OC-12, OC-48, Gigabit Ethernet, and 15/14 FEC rates. All SONET Adjustable slice level: 100 mV jitter requirements are met, including jitter transfer, jitter 1.9 GHz minimum bandwidth generation, and jitter tolerance. All specifications are quoted for Patented clock recovery architecture 40C to +85C ambient temperature, unless otherwise noted. Loss of signal detect range: 3 mV to 15 mV The device is intended for WDM system applications, and can Single reference clock frequency for all rates, including be used with either an external reference clock or an on-chip 15/14 (7%) wrapper rate oscillator with external crystal. Both native rates and 15/14 rate Choice of 19.44 MHz, 38.88 MHz, 77.76 MHz, or 155.52 MHz digital wrappers are supported by the ADN2819, without any REFCLK change of reference clock. LVPECL/LVDS/LVCMOS/LVTTL compatible inputs This device, together with a PIN diode and a TIA preamplifier, (LVPECL/LVDS only at 155.52 MHz) can implement a highly integrated, low cost, low power, fiber 19.44 MHz oscillator on-chip to be used with external crystal optic receiver. Loss of lock indicator Loopback mode for high speed test data The receiver front end signal detect circuit indicates when the Output squelch and bypass features input signal level has fallen below a user-adjustable threshold. Single-supply operation: 3.3 V The signal detect circuit has hysteresis to prevent chatter at the Low power: 540 mW typical output. 7 mm 7 mm 48-lead LFCSP The ADN2819 is available in a compact 7 mm 7 mm, 48-lead APPLICATIONS chip scale package. SONET OC-3/-12/-48, SDH STM-1/-4/-16, GbE and 15/14 FEC rates WDM transponders Regenerators/repeaters Test equipment Backplane applications FUNCTIONAL BLOCK DIAGRAM SLICEP/N VCC VEE LOL CF1 CF2 ADN2819 2 LOOP 2 FILTER REFSEL 0..1 PIN 2 /n REFCLKP/N FREQUENCY PHASE LOOP PHASE QUANTIZER XO1 VCO LOCK SHIFTER FILTER DET. DETECTOR NIN XTAL OSC XO2 FRACTIONAL DIVIDER VREF REFSEL LEVEL DATA DIVIDER DETECT RETIMING 1/2/4/16 3 2 2 THRADJ SDOUT DATAOUTP/N CLKOUTP/N SEL 0..2 Figure 1. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20032016 Analog Devices, Inc. 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Technical Support www.analog.com 02999-0-001ADN2819 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Functional Description .................................................................. 15 Applications ....................................................................................... 1 Multirate Clock and Data Recovery ........................................ 15 Product Description ......................................................................... 1 Limiting Amplifier ..................................................................... 15 Functional Block Diagram .............................................................. 1 Slice Adjust .................................................................................. 15 Revision History ............................................................................... 2 Loss of Signal (LOS) Detector .................................................. 15 Specifications ..................................................................................... 3 Reference Clock .......................................................................... 15 Absolute Maximum Ratings ............................................................ 6 Lock Detector Operation .......................................................... 16 Thermal Characteristics .............................................................. 6 Squelch Mode ............................................................................. 17 ESD Caution .................................................................................. 6 Test Modes: Bypass and Loopback ........................................... 17 Pin Configuration and Function Descriptions ............................. 7 Applications Information .............................................................. 18 Definition of Terms ........................................................................ 10 PCB Design Guidelines ............................................................. 18 Maximum, Minimum, and Typical Specifications................. 10 Choosing AC-Coupling Capacitors ......................................... 20 Input Sensitivity and Input Overdrive ..................................... 10 DC-Coupled Application .......................................................... 21 Single-Ended vs. Differential .................................................... 10 LOL Toggling During Loss of Input Data ............................... 21 LOS Response Time ................................................................... 11 Outline Dimensions ....................................................................... 22 Jitter Specifications ..................................................................... 11 Ordering Guide .......................................................................... 22 Theory of Operation ...................................................................... 13 REVISION HISTORY 5/16Rev. B to Rev. C Changes to Figure 2 and Table 3 ..................................................... 7 Changes to Figure 22 ...................................................................... 18 Updated Outline Dimensions ....................................................... 21 Changes to Ordering Guide .......................................................... 21 5/04Rev. A to Rev. B Updated Format .................................................................. Universal Changes to Specifications ................................................................ 3 Changes to Table 7 and Table 8 ..................................................... 15 Updated Outline Dimensions ....................................................... 21 Changes to Ordering Guide .......................................................... 21 1/03Rev. 0 to Rev. A Changes to Table IV ....................................................................... 12 Updated Outline Dimensions ....................................................... 16 Rev. C Page 2 of 25