Multirate 155 Mbps/622 Mbps/1244 Mbps/1250 Mbps Burst Mode Clock and Data Recovery IC with Deserializer Data Sheet ADN2855 FEATURES GENERAL DESCRIPTION Serial data input The ADN2855 is a burst mode clock and data recovery IC 155.52 Mbps/622.08 Mbps/1244.16 Mbps/1250.00 Mbps designed for GPON/BPON/GEPON optical line terminal (OLT) 12-bit acquisition time receiver applications. The part can operate at 155.52 Mbps, 4-bit parallel LVDS output interface 622.08 Mbps, 1244.16 Mbps, or 1250.00 Mbps data rates, selectable 2 Patented dual-loop clock recovery architecture via the I C interface. Integrated PRBS generator The ADN2855 frequency locks to the OLT reference clock and Byte rate reference clock aligns to the input data within 12 bits of the start of the preamble. Loss-of-lock indicator The device provides a full rate or an optional half rate output Supports double data rate (DDR)-compatible FPGA clock for a double data rate (DDR) interface to an FPGA or 2 I C interface to access optional features digital ASIC. Single-supply operation: 3.3 V All specifications are quoted for 40C to +85C ambient tempera- Power ture, unless otherwise noted. The ADN2855 is available in a 670 mW typical in serial output mode compact 5 mm 5 mm, 32-lead chip scale package. 825 mW typical in deserializer mode 5 mm 5 mm, 32-lead LFCSP APPLICATIONS Passive optical networks GPON/BPON/GEPON OLT receivers FUNCTIONAL BLOCK DIAGRAM REFCLKP, DATAV CF1 CF2 VCC VEE REFCLKN ADN2855 LOOP FREQUENCY/ FILTER LOCK RESET DETECT PIN CML INPUT PHASE PHASE LOOP VCO BUFFER SHIFTER DETECT FILTER NIN DATA RE-TIMING 2 SDA 2 I C SCK DIVIDER DESERIALIZER SQUELCH 4 2 2 DATxP, CLKOUTP, DATxN CLKOUTN Figure 1. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20092017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 06660-001ADN2855 Data Sheet TABLE OF CONTENTS 2 Features .............................................................................................. 1 I C Interface Timing and Internal Register Description ..............9 Applications ....................................................................................... 1 Theory of Operation ...................................................................... 11 General Description ......................................................................... 1 Functional Description .................................................................. 12 Functional Block Diagram .............................................................. 1 Frequency Acquisition ............................................................... 12 Revision History ............................................................................... 2 Squelch Mode ............................................................................. 12 2 Specif icat ions ..................................................................................... 3 I C Interface ................................................................................ 12 Jitter Specifications ....................................................................... 3 Reference Clock .......................................................................... 13 Output and Timing Specifications ............................................. 4 Output Modes ............................................................................. 14 Timing Characteristcs .................................................................. 5 Disable Output Buffers .............................................................. 14 Reset Timing Options .................................................................. 6 Applications Information .............................................................. 15 Absolute Maximum Ratings ............................................................ 7 PCB Design Guidelines ............................................................. 15 Thermal Resistance ...................................................................... 7 Outline Dimensions ....................................................................... 17 ESD Caution .................................................................................. 7 Ordering Guide .......................................................................... 17 Pin Configuration and Function Descriptions ............................. 8 REVISION HISTORY 4/2017Rev. A to Rev. B Changed CP-32-13 to CP-32-20 .................................. Throughout Changes to Soldering Guidelines for Chip Scale Package Section ........................................................................................................ 16 Updated Outline Dimensions ....................................................... 17 Changes to Ordering Guide .......................................................... 17 2/2013Rev. 0 to Rev. A Change to Table 5 ............................................................................. 7 Updated Outline Dimensions ....................................................... 17 Changes to Ordering Guide .......................................................... 17 1/2009Revision 0: Initial Version Rev. B Page 2 of 20