Continuous Rate 6.5 Mbps to 8.5 Gbps Clock and Data Recovery IC with Integrated Limiting Amp/EQ Data Sheet ADN2913 FEATURES GENERAL DESCRIPTION Serial data input: 6.5 Mbps to 8.5 Gbps The ADN2913 provides the receiver functions of quantization, No reference clock required signal level detection, and clock and data recovery for continuous Exceeds SONET/SDH requirements for jitter transfer/ data rates from 6.5 Mbps to 8.5 Gbps. The ADN2913 automatically generation/tolerance locks to all data rates without the need for an external reference Quantizer sensitivity: 6.3 mV typical (limiting amplifier mode) clock or programming. ADN2913 jitter performance exceeds all Optional limiting amplifier, equalizer (EQ), and 0 dB EQ inputs jitter specifications required by SONET/SDH, including jitter Programmable jitter transfer bandwidth to support G.8251 OTN transfer, jitter generation, and jitter tolerance. Programmable slice level The ADN2913 provides manual or automatic slice adjust and Sample phase adjust (5.65 Gbps or greater) manual sample phase adjusts. Additionally, the user can select a Output polarity invert 2 limiting amplifier, equalizer, or 0 dB EQ at the input. The equalizer Programmable LOS threshold via I C 2 is adaptive or it can be manually set. I C interface to access optional features Loss of signal (LOS) alarm (limiting amplifier mode only) The receiver front-end loss of signal (LOS) detector Loss of lock (LOL) indicator circuit indicates when the input signal level falls below a user- PRBS generator/detector programmable threshold. The LOS detection circuit has hysteresis Application aware power to prevent chatter at the LOS output. In addition, the input signal 2 352 mW at 8.5 Gbps, equalizer mode, no clock output strength can be read through the I C registers. 380 mW at 6.144 Gbps, limiting amplifier mode, The ADN2913 also supports pseudorandom binary sequence no clock output (PRBS) generation, bit error detection, and input data rate 340 mW at 622 Mbps, 0 dB EQ mode, no clock output readback features. Power supplies: 1.2 V, flexible 1.8 V to 3.3 V, and 3.3 V The ADN2913 is available in a compact 4 mm 4 mm, 24-lead 4 mm 4 mm, 24-lead LFCSP lead frame chip scale package (LFCSP). All ADN2913 specifica- APPLICATIONS tions are defined over the ambient temperature range of 40C SONET/SDH OC-1/OC-3/OC-12/OC-48 and all associated to +85C, unless otherwise noted. FEC rates 1GE, 1GFC, 2GFC, 4GFC, 8GFC, CPRI OS/L.6 up to OS/L.60 Any rate regenerators/repeaters FUNCTIONAL BLOCK DIAGRAM REFCLKP/ REFCLKN DATOUTP/ CLKOUTP/ SCK SDA LOL (OPTIONAL) DATOUTN CLKOUTN DATA RATE 2 2 I C REGISTERS I C ADDR FREQUENCY CML CML ACQUISITION AND LOCK DETECTOR CLK DDR ADN2913 LOS LOS SAMPLE FIFO DETECT PHASE N 2 ADJUST DOWNSAMPLER DCO LA AND LOOP DATA FILTER PIN 2 INPUT RXD 0dB EQ NIN SAMPLER RXCK EQ 50 50 CLOCK 2 I C PHASE 2 I C SHIFTER V V CM CC FLOAT Figure 1. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20132017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com SLICE ADJUST LOS THRESH TXD 11777-001ADN2913 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Limiting Amplifier ..................................................................... 22 Applications ....................................................................................... 1 Slice Adjust .................................................................................. 22 General Description ......................................................................... 1 Edge Select ................................................................................... 22 Functional Block Diagram .............................................................. 1 Loss of Signal (LOS) Detector .................................................. 23 Revision History ............................................................................... 2 Passive Equalizer ........................................................................ 24 Specifications ..................................................................................... 3 0 dB EQ ........................................................................................ 24 Jitter Specifications ....................................................................... 5 Lock Detector Operation .......................................................... 26 Output and Timing Specifications ............................................. 6 Harmonic Detector .................................................................... 26 Timing Diagrams .......................................................................... 8 Output Disable and Squelch ..................................................... 27 2 Absolute Maximum Ratings ............................................................ 9 I C Interface ................................................................................ 27 Thermal Characteristics .............................................................. 9 Reference Clock (Optional) ...................................................... 27 2 ESD Caution .................................................................................. 9 Additional Features Available via the I C Interface ............... 29 Pin Configuration and Function Descriptions ........................... 10 Input Configurations ................................................................. 31 Typical Performance Characteristics ........................................... 11 Applications Information .............................................................. 34 2 I C Interface Timing and Internal Register Descriptions ......... 13 Transmission Lines..................................................................... 34 Register Map ............................................................................... 14 Soldering Guidelines for Lead Frame Chip Scale Package ... 34 Theory of Operation ...................................................................... 20 Outline Dimensions ....................................................................... 35 Functional Description .................................................................. 22 Ordering Guide .......................................................................... 35 Frequency Acquisition ............................................................... 22 REVISION HISTORY 8/2017Rev. A to Rev. B Changed CP-24-14 to CP-24-7 .................................... Throughout Updated Outline Dimensions ....................................................... 34 Changes to Ordering Guide .......................................................... 34 2/2016Rev. 0 to Rev. A Changes to Figure 5 ........................................................................ 10 Changes to Table 7 .......................................................................... 15 Updated Outline Dimensions ....................................................... 33 Changes to Ordering Guide .......................................................... 33 12/2013Revision 0: Initial Version Rev. B Page 2 of 35