Continuous Rate 6.5 Mbps to 11.3 Gbps Clock and Data Recovery IC with Integrated Limiting Amp/EQ Data Sheet ADN2915 FEATURES GENERAL DESCRIPTION Serial data input: 6.5 Mbps to 11.3 Gbps The ADN2915 provides the receiver functions of quantization, No reference clock required signal level detect, and clock and data recovery for continuous Exceeds SONET/SDH requirements for jitter data rates from 6.5 Mbps to 11.3 Gbps. The ADN2915 automati- transfer/generation/tolerance cally locks to all data rates without the need for an external Quantizer sensitivity: 7.3 mV typical (limiting amplifier mode) reference clock or programming. ADN2915 jitter performance Optional limiting amplifier, equalizer, and bypass inputs exceeds all jitter specifications required by SONET/SDH, including Programmable jitter transfer bandwidth to support G.8251 OTN jitter transfer, jitter generation, and jitter tolerance. Programmable slice level The ADN2915 provides manual or automatic slice adjust and Sample phase adjust (5.65 Gbps or greater) manual sample phase adjusts. Additionally, the user can select a Output polarity invert 2 limiting amplifier, equalizer, or bypass at the input. The equalizer Programmable LOS threshold via I C 2 is either adaptive or can be manually set. I C to access optional features Loss of signal (LOS) alarm (limiting amplifier mode only) The receiver front-end loss of signal (LOS) detector circuit Loss of lock (LOL) indicator indicates when the input signal level has fallen below a user- PRBS generator/detector programmable threshold. The LOS detect circuit has hysteresis Application-aware power to prevent chatter at the LOS output. In addition, the input 2 430 mW at 11.3 Gbps, equalizer enabled, no clock output signal strength can be read through the I C registers. 380 mW at 6.144 Gbps, limiting amplifier mode, no clock The ADN2915 also supports pseudorandom binary sequence output (PRBS) generation, bit error detection, and input data rate 340 mW at 622 Mbps, input bypass mode, no clock output readback features. Power supply: 1.2 V, flexible 1.8 V to 3.3 V, and 3.3 V The ADN2915 is available in a compact 4 mm 4 mm, 24-lead 4 mm 4 mm 24-lead LFCSP chip scale package (LFCSP). All ADN2915 specifications are APPLICATIONS defined over the ambient temperature range of 40C to +85C, SONET/SDH OC-1/OC-3/OC-12/OC-48/OC-192 and all unless otherwise noted. associated FEC rates 1GFC, 2GFC, 4GFC, 8GFC, 10GFC, 1GE, and 10GE WDM transponders Any rate regenerators/repeaters FUNCTIONAL BLOCK DIAGRAM REFCLKP/ REFCLKN DATOUTP/ CLKOUTP/ SCK SDA LOL (OPTIONAL) DATOUTN CLKOUTN DATA RATE 2 2 I C REGISTERS I C ADDR FREQUENCY CML CML ACQUISITION AND LOCK DETECTOR CLK DDR ADN2915 LOS LOS SAMPLE FIFO DETECT PHASE N 2 ADJUST DOWNSAMPLER DCO LA AND LOOP DATA FILTER PIN 2 RXD INPUT BYPASS NIN SAMPLER RXCK EQ 50 50 CLOCK 2 I C PHASE 2 I C SHIFTER V V CM CC FLOAT Figure 1. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20132016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. SLICE ADJUST LOS THRESH TXD 08413-001ADN2915 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Frequency Acquisition ............................................................... 22 Applications ....................................................................................... 1 Limiting Amplifier ..................................................................... 22 General Description ......................................................................... 1 Slice Adjust .................................................................................. 22 Functional Block Diagram .............................................................. 1 Edge Select ................................................................................... 22 Revision History ............................................................................... 2 Loss of Signal (LOS) Detector .................................................. 23 Specifications ..................................................................................... 3 Passive Equalizer ........................................................................ 24 Jitter Specifications ....................................................................... 5 Bypass........................................................................................... 24 Output and Timing Specifications ............................................. 6 Lock Detector Operation .......................................................... 25 Timing Diagrams .......................................................................... 8 Harmonic Detector .................................................................... 25 Absolute Maximum Ratings ............................................................ 9 Output Disable and Squelch ..................................................... 26 2 Thermal Characteristics .............................................................. 9 I C Interface ................................................................................ 26 ESD Caution .................................................................................. 9 Reference Clock (Optional) ...................................................... 26 2 Pin Configuration and Function Descriptions ........................... 10 Additional Features Available via the I C Interface ............... 28 Typical Performance Characteristics ........................................... 11 Input Configurations ................................................................. 30 2 I C Interface Timing and Internal Register Descriptions ......... 14 DC-Coupled Application .......................................................... 32 Register Map ............................................................................... 15 Outline Dimensions ....................................................................... 33 Theory of Operation ...................................................................... 20 Ordering Guide .......................................................................... 33 Functional Description .................................................................. 22 REVISION HISTORY 1/16Rev. 0 to Rev. A Changed NC to DNC .................................................... Throughout Changes to Figure 5 ........................................................................ 10 Updated Outline Dimensions ....................................................... 33 Changes to Ordering Guide .......................................................... 33 7/13Revision 0: Initial Version Rev. A Page 2 of 36