5 kV RMS and 3.75 kV RMS, Dual-Channel LVDS Gigabit Isolators Data Sheet ADN4654/ADN4655/ADN4656 FEATURES FUNCTIONAL BLOCK DIAGRAMS V V IN1 IN2 5 kV rms and 3.75 kV rms LVDS isolators ADN4654 Complies with TIA/EIA-644-A LVDS standard ISOLATION LDO LDO BARRIER Multiple dual-channel configurations V V DD1 DD2 Any data rate up to 1.1 Gbps switching with low jitter D D IN1+ OUT1+ 4 ns typical propagation delay D D IN1 OUT1 2.6 ps rms typical random jitter, rms LVDS DIGITAL ISOLATOR LVDS 90 ps typical peak-to-peak total jitter at 1.1 Gbps D D IN2+ OUT2+ 2.5 V or 3.3 V supplies D IN2 D OUT2 75 dBc power supply ripple rejection, phase spur level GND GND Glitch immunity 1 2 8 kV IEC 61000-4-2 ESD protection across isolation barrier Figure 1. V V High common-mode transient immunity: >25 kV/s IN1 IN2 Passes EN 55022 Class B radiated emissions limits with ADN4655 ISOLATION LDO LDO BARRIER 1.1 Gbps PRBS V V DD1 DD2 Safety and regulatory approvals (20-lead SOIC W package) D D IN1+ OUT1+ UL (pending): 5000 V rms for 1 minute per UL 1577 D D IN1 OUT1 CSA Component Acceptance Notice 5A (pending) LVDS DIGITAL ISOLATOR LVDS VDE certificate of conformity (pending) D D OUT2+ IN2+ DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 D D OUT2 IN2 V = 424 V IORM PEAK Fail-safe output high for open, short, and terminated input GND GND 1 2 conditions (ADN4655/ADN4656) Figure 2. Operating temperature range: 40C to +125C V V IN1 IN2 7.8 mm minimum creepage and clearance ADN4656 ISOLATION LDO LDO BARRIER APPLICATIONS V V DD1 DD2 Isolated video and imaging data D D OUT1+ IN1+ Analog front-end isolation D D OUT1 IN1 LVDS DIGITAL ISOLATOR LVDS Data plane isolation D D IN2+ OUT2+ Isolated high speed clock and data links D D OUT2 IN2 GND GND 1 2 Figure 3. GENERAL DESCRIPTION 1 The ADN4654/ADN4655/ADN4656 are signal isolated, low 1 on the corresponding LVDS driver output when the inputs are voltage differential signaling (LVDS) buffers that operate at up floating, shorted, or terminated but not driven. to 1.1 Gbps with low jitter. The devices integrate Analog For high speed operation with low jitter, the LVDS and isolator Devices, Inc., iCoupler technology, enhanced for high speed circuits rely on a 2.5 V supply. An integrated on-chip low dropout operation to provide galvanic isolation of the TIA/EIA-644-A (LDO) regulator can provide the required 2.5 V from an external compliant LVDS drivers and receivers. This integration allows 3.3 V power supply. The devices are fully specified over a wide drop-in isolation of an LVDS signal chain. industrial temperature range and come in a 20-lead, wide body The ADN4654/ADN4655/ADN4656 comprise multiple SOIC W package with 5 kV rms isolation or in a 20-lead SSOP channel configurations, and the LVDS receivers on the ADN4655 package with 3.75 kV rms isolation. and ADN4656 include a fail-safe mechanism to ensure a Logic 1 Protected by U.S. Patents 5,952,849 6,873,065 6,903,578 and 7,075,329. Other patents are pending. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20182019 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 17 011-0 01 17011-050 17 011-1 02ADN4654/ADN4655/ADN4656 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 ESD Caution...................................................................................8 Applications ....................................................................................... 1 Pin Configurations and Function Descriptions ............................9 Functional Block Diagrams ............................................................. 1 Typical Performance Characteristics ........................................... 12 General Description ......................................................................... 1 Test Circuits and Switching Characteristics ................................ 17 Revision History ............................................................................... 2 Theory of Operation ...................................................................... 18 Specif icat ions ..................................................................................... 3 Truth Table and Fail-Safe Receiver .......................................... 18 Receiver Input Threshold Test Voltages .................................... 4 Isolation ....................................................................................... 19 Timing Specifications .................................................................. 4 Applications Information .............................................................. 20 Insulation and Safety Related Specifications ............................ 5 PCB Layout ................................................................................. 20 Package Characteristics ............................................................... 6 Application Examples ................................................................ 20 Regulatory Information ............................................................... 6 Magnetic Field Immunity .......................................................... 22 DIN V VDE V 0884-10 (VDE V 0884-10) Insulation Insulation Lifetime ..................................................................... 22 Characteristics (Pending) ............................................................ 7 Outline Dimensions ....................................................................... 24 Recommended Operating Conditions ...................................... 7 Ordering Guide .......................................................................... 25 Absolute Maximum Ratings ............................................................ 8 Thermal Resistance ...................................................................... 8 REVISION HISTORY 9/2019Rev. C to Rev. D 1/2019Rev. 0 to Rev. A Added ADN4655 ................................................................ Universal Changes to Ordering Guide .......................................................... 25 Added Figure 2 Renumbered Sequentially ................................... 1 6/2019Rev. B to Rev. C Changes to General Description Section ....................................... 1 Added ADN4656 ................................................................ Universal Changes to Table 1 ............................................................................. 3 Changes to Features Section............................................................ 1 Changes to Table 3 ............................................................................. 4 Added Figure 3 Renumbered Sequentially .................................. 1 Added Timing Diagram Section and Figure 3 .............................. 5 Added Note 1, Table 8 ...................................................................... 7 Changes to Figure 5 Caption and Table 12 Title ........................... 9 Added Figure 8 and Table 15 Renumbered Sequentially ......... 11 Added Figure 6 and Table 13 Renumbered Sequentially ......... 10 Changes to Theory of Operation Section and Truth Table and Changes to Magnetic Field Immunity Section ........................... 22 Changes to Ordering Guide .......................................................... 25 Fail Safe Receiver Section .............................................................. 17 Added Table 15 ............................................................................... 17 3/2019Rev. A to Rev. B Moved Isolation Section ................................................................ 18 Changes to Title, Features Section, General Description Moved PCB Layout Section .......................................................... 19 Section, and Figure 2 ........................................................................ 1 Changes to PCB Layout Section ................................................... 19 Changes to Table 4 ............................................................................ 5 Changes to Ordering Guide .......................................................... 23 Added Table 5 .................................................................................... 5 11/2018Revision 0: Initial Version Changes to Table 7 ............................................................................ 6 Changes to Table 8 and Figure 4 ..................................................... 7 Changes to Table 10, Table 11, and Table 12 ................................. 8 Added Figure 44 .............................................................................. 23 Changes to Ordering Guide .......................................................... 23 Rev. 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