Data Sheet ADN4680E 250 Mbps, Half-Duplex, Quad M-LVDS Transceivers FEATURES FUNCTIONAL BLOCK DIAGRAM Four M-LVDS transceivers (driver and receiver pairs) Switching rate: 250 Mbps (125 MHz) Independent pin select for each receiver, two modes: Type 1: input hysteresis of 15 mV typical Type 2: differential input threshold voltage offset by 100 mV to support open-circuit, short-circuit, and bus idle fail-safe Compatible with the TIA/EIA-899 standard for M-LVDS Glitch free power-up/power-down on the M-LVDS bus Controlled transition times on the driver output Common-mode range: 1 V to +3.4 V, allowing communication with 2 V of ground noise Driver outputs high-Z when disabled or powered off Independent enable pins for each driver and receiver Enhanced ESD protection on bus pins 15 kV HBM, air discharge 8 kV HBM, contact discharge 10 kV IEC 61000-4-2, air discharge 8 kV IEC 61000-4-2, contact discharge Figure 1. Enhanced 8 kV HBM ESD protection for all pins, contact dis- GENERAL DESCRIPTION charge Operating temperature range: 40C to +105C The ADN4680E comprises four multipoint, low voltage differential Available in 48-lead, 7 mm x 7 mm LFCSP signaling (M-LVDS) transceivers (driver and receiver pairs) that can operate at up to 125 MHz, or 250 Mbps nonreturn to zero APPLICATIONS (NRZ). The driver and receiver of each transceiver are connected in half-duplex configuration, which allows each transceiver to be con- Backplane and cable multipoint data transmission figured via independent enable pins for either sending or receiving Multipoint clock distribution data. Electrostatic discharge (ESD) protection of up to 15 kV is im- Low power, high speed alternative to shorter RS-485 links plemented on the bus pins. The transceivers are optimized for low Networking and wireless base station infrastructure dynamic power consumption for use in high density applications. Grid infrastructure and relay protection systems The ADN4680E is designed to the TIA/EIA-899 standard for use in M-LVDS networks and complement TIA/EIA-644 LVDS devices with Differential extension of SPI networks additional multipoint capabilities. The receivers detect the bus state with a differential input of as little as 50 mV over a common-mode voltage range of 1 V to +3.4 V. Each receiver can be independently pin selectable as a Type 1 or Type 2 receiver. Type 1 receivers have 15 mV of hystere- sis so that slow changing signals or loss of input does not lead to output oscillations. Type 2 receivers exhibit an offset threshold, guaranteeing the output state when the inputs are open (open circuit fail-safe), the bus is idle (bus idle or terminated fail-safe), or when the inputs are hard short circuited. The device is available in a compact 48-lead, 7 mm 7 mm LFCSP and operates over a temperature range of 40C to +105C. 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Trademarks and TECHNICAL SUPPORT registered trademarks are the property of their respective owners.Data Sheet ADN4680E TABLE OF CONTENTS Features................................................................ 1 Receiver Timing Measurements.......................15 Applications........................................................... 1 Theory of Operation.............................................16 Functional Block Diagram......................................1 Three-State Bus Connection............................16 General Description...............................................1 Truth Tables......................................................16 Specifications........................................................ 3 Glitch Free Powering Up and Powering Receiver Input Threshold Test Voltages.............4 Down.............................................................. 17 Timing Specifications......................................... 5 Fault Conditions............................................... 17 Absolute Maximum Ratings...................................7 Receiver Input Thresholds and Fail-Safe.........17 Thermal Resistance........................................... 7 Sixty-Four Transceivers on a Network............. 17 Electrostatic Discharge (ESD) Ratings...............7 Applications Information...................................... 18 ESD Caution.......................................................7 PCB Layout...................................................... 19 Pin Configurations and Function Descriptions.......8 M-LVDS Design Considerations.......................19 Typical Performance Characteristics.....................9 Extending the SPI over M-LVDS...................... 19 Test Circuits and Switching Characteristics.........13 Outline Dimensions............................................. 21 Driver Voltage and Current Measurements......13 Ordering Guide.................................................21 Driver Timing Measurements........................... 14 Evaluation Boards............................................ 21 REVISION HISTORY 9/2021Revision 0: Initial Version analog.com Rev. 0 2 of 21