3.3 V, 100 Mbps, Half- and Full-Duplex, High Speed M-LVDS Transceivers Data Sheet ADN4690E/ADN4692E/ADN4694E/ADN4695E FEATURES FUNCTIONAL BLOCK DIAGRAMS V Multipoint LVDS transceivers (low voltage differential CC signaling driver and receiver pairs) ADN4690E/ Switching rate: 100 Mbps (50 MHz) ADN4694E Supported bus loads: 30 to 55 RO R Choice of 2 receiver types RE A Type 1 (ADN4690E/ADN4692E): hysteresis of 25 mV B DE Type 2 (ADN4694E/ADN4695E): threshold offset of 100 mV DI D for open-circuit and bus-idle fail-safe Conforms to TIA/EIA-899 standard for M-LVDS GND Glitch-free power-up/power-down on M-LVDS bus Figure 1. Controlled transition times on driver output Common-mode range: 1 V to +3.4 V, allowing V CC communication with 2 V of ground noise Driver outputs high-Z when disabled or powered off ADN4692E/ Enhanced ESD protection on bus pins ADN4695E A 15 kV HBM (human body model), air discharge RO R B 8 kV HBM (human body model), contact discharge RE 10 kV IEC 61000-4-2, air discharge DE Z 8 kV IEC 61000-4-2, contact discharge D DI Y Operating temperature range: 40C to +85C Available in 8-lead (ADN4690E/ADN4694E) and 14-lead GND (ADN4692E/ADN4695E) SOIC packages Figure 2. APPLICATIONS Backplane and cable multipoint data transmission Multipoint clock distribution Low power, high speed alternative to shorter RS-485 links Networking and wireless base station infrastructure GENERAL DESCRIPTION The ADN4690E/ADN4692E/ADN4694E/ADN4695E are The parts are available as half-duplex in an 8-lead SOIC package multipoint, low voltage differential signaling (M-LVDS) (the ADN4690E/ADN4694E) or as full-duplex in a 14-lead transceivers (driver and receiver pairs) that can operate at up SOIC package (the ADN4692E/ADN4695E). A selection table for the ADN469xE parts is shown in Table 1. to 100 Mbps (50 MHz). Slew rate control is implemented on the driver outputs. The receivers detect the bus state with a differential Table 1. High Speed M-LVDS Transceiver Selection Table input of as little as 50 mV over a common-mode voltage range of Part No. Receiver Data Rate SOIC Duplex 1 V to +3.4 V. ESD protection of up to 15 kV is implemented ADN4690E Type 1 100 Mbps 8-lead Half on the bus pins. The parts adhere to the TIA/EIA-899 standard for ADN4691E Type 1 200 Mbps 8-lead Half M-LVDS and complement TIA/EIA-644 LVDS devices with ADN4692E Type 1 100 Mbps 14-lead Full additional multipoint capabilities. ADN4693E Type 1 200 Mbps 14-lead Full The ADN4690E/ADN4692E are Type 1 receivers with 25 mV of ADN4694E Type 2 100 Mbps 8-lead Half hysteresis, so that slow-changing signals or loss of input does ADN4695E Type 2 100 Mbps 14-lead Full not lead to output oscillations. The ADN4694E/ADN4695E are ADN4696E Type 2 200 Mbps 8-lead Half Type 2 receivers exhibiting an offset threshold, guaranteeing the ADN4697E Type 2 200 Mbps 14-lead Full output state when the bus is idle (bus-idle fail-safe) or the inputs are open (open-circuit fail-safe). Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20122016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 10471-102 10471-001ADN4690E/ADN4692E/ADN4694E/ADN4695E Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Driver Voltage and Current Measurements ............................ 11 Applications ....................................................................................... 1 Driver Timing Measurements .................................................. 12 Functional Block Diagrams ............................................................. 1 Receiver Timing Measurements ............................................... 13 General Description ......................................................................... 1 Theory of Operation ...................................................................... 14 Revision History ............................................................................... 2 Half-Duplex/Full-Duplex Operation ....................................... 14 Specifications ..................................................................................... 3 Three-State Bus Connection ..................................................... 14 Receiver Input Threshold Test Voltages .................................... 4 Truth Tables................................................................................. 14 Timing Specifications .................................................................. 5 Glitch-Free Power-Up/Power-Down ....................................... 15 Absolute Maximum Ratings ............................................................ 6 Fault Conditions ......................................................................... 15 Thermal Resistance ...................................................................... 6 Receiver Input Thresholds/Fail-Safe ........................................ 15 ESD Caution .................................................................................. 6 Applications Information .............................................................. 16 Pin Configurations and Function Descriptions ........................... 7 Outline Dimensions ....................................................................... 17 Typical Performance Characteristics ............................................. 8 Ordering Guide .......................................................................... 17 Test Circuits and Switching Characteristics ................................ 11 REVISION HISTORY 1/16Rev. A to Rev. B Added Table 4, Renumbered Sequentially ..................................... 5 Changed NC to DNC .................................................... Throughout Added Type 2 Receiver Parameters, Table 5 .................................. 5 Changes to Table 1 Title ................................................................... 1 Changes to Table 8 ............................................................................. 7 Changes to Table 6 ............................................................................ 6 Added Table 13 ............................................................................... 14 Changes to Receiver Input Thresholds/Fail-Safe Section 3/12Rev. 0 to Rev. A and Figure 35 ................................................................................... 15 Added ADN4694E and ADN4695E ................................. Universal Changes to Figure 36 and Figure 37 and Their Captions ......... 16 Change to Features Section, General Description Section, Changes to Ordering Guide .......................................................... 18 and Table 1 ......................................................................................... 1 Added Type 2 Receiver Parameters, Table 2 ................................. 3 1/12Revision 0: Initial Version Rev. B Page 2 of 20