Thermoelectric Cooler Controller ADN8830 FEATURES GENERAL DESCRIPTION High Efficiency The ADN8830 is a monolithic controller that drives a thermo- Small Size: 5 mm 5 mm LFCSP electric cooler (TEC) to stabilize the temperature of a laser diode Low Noise: <0.5% TEC Current Ripple or a passive component used in telecommunications equipment. Long-Term Temperature Stability: 0.01 C This device relies on a negative temperature coefficient (NTC) Temperature Lock Indication thermistor to sense the temperature of the object attached to the Temperature Monitoring Output TEC. The target temperature is set with an analog input voltage Oscillator Synchronization with an External Signal either from a DAC or an external resistor divider. Clock Phase Adjustment for Multiple Controllers The loop is stabilized by a PID compensation amplifier with Programmable Switching Frequency up to 1 MHz high stability and low noise. The compensation network can be Thermistor Failure Alarm adjusted by the user to optimize temperature settling time. The Maximum TEC Voltage Programmability component values for this network can be calculated based on APPLICATIONS the thermal transfer function of the laser diode or obtained Thermoelectric Cooler (TEC) Temperature Control from the lookup table given in the Application Notes section. Resistive Heating Element Control Voltage outputs are provided to monitor both the temperature of Temperature Stabilization Substrate (TSS) Control the object and the voltage across the TEC. A voltage reference of 2.5 V is also provided. FUNCTIONAL BLOCK DIAGRAM PID COMPENSATION NETWORK P-CHANNEL FROM (UPPER MOSFET) THERMISTOR TEMPERATURE PWM MEASUREMENT N-CHANNEL CONTROLLER AMPLIFIER TEMPERATURE MOSFET SET DRIVERS INPUT P-CHANNEL (LOWER MOSFET) VOLTAGE OSCILLATOR V REF REFERENCE N-CHANNEL FREQUENCY/PHASE CONTROL D REV. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700 www.analog.com under any patent or patent rights of Analog Devices. Trademarks and 781/461-3113 2012 registered trademarks are the property of their respective owners. Fax: Analog Devices, Inc. All rights reserved.( V = 3.3 V to 5.0 V, V = 0 V, T = 25 C, T = 25 C, using typical application DD GND A SET ADN8830SPECIFICATIONS configuration as shown in Figure 1, unless otherwise noted.) Parameter Symbol Conditions Min Typ Max Unit TEMPERATURE STABILITY Long-Term Stability Using 10 k thermistor with = 4.4% at 25C 0.01 C PWM OUTPUT DRIVERS Output Transition Time t , t C = 3,300 pF 20 ns R F L Nonoverlapping Clock Delay 50 65 ns Output Resistance R (N1, P1) I = 50 mA 6 O L Output Voltage Swing OUT A V = 0 V 0 V V LIM DD Output Voltage Ripple OUT A f = 1 MHz 0.2 % CLK Output Current Ripple I f = 1 MHz 0.2 % TEC CLK LINEAR OUTPUT AMPLIFIER Output Resistance R I = 2 mA 85 O, P2 OUT R I = 2 mA 178 O, N2 OUT Output Voltage Swing OUT B 0 V V DD POWER SUPPLY Power Supply Voltage V 3.0 5.5 V DD Power Supply Rejection Ratio PSRR V = 3.3 V to 5 V, V = 0 V 80 92 dB DD TEC 40C T +85C60 dB A Supply Current I PWM not switching 8 12 mA SY 40C T +85C15mA A Shutdown Current I Pin 10 = 0 V 5 A SD Soft-Start Charging Current I 15 A SS Undervoltage Lockout V Low-to-high threshold 2.0 2.7 V OLOCK ERROR AMPLIFIER Input Offset Voltage V V = 1.5 V 50 250 V OS CM Gain A 20 V/V V, IN Input Voltage Range V 0.2 2.0 V CM Common-Mode Rejection Ratio CMRR 0.2 V < V < 2.0 V 58 68 dB CM 40C T +85C55 dB A Open-Loop Input Impedance R 1G IN Gain-Bandwidth Product GBW 2 MHz REFERENCE VOLTAGE Reference Voltage V I < 2 mA 2.37 2.47 2.57 V REF REF OSCILLATOR Synchronization Range f Pin 25 connected to external clock 200 1,000 kHz CLK Oscillator Frequency f Pin 24 = V (R = 150 k 800 1,000 1,250 kHz CLK DD Pin 25 = GND) LOGIC CONTROL* Logic Low Input Threshold 0.2 V Logic High Input Threshold 3 V Logic Low Output Level 0.2 V Logic High Output Threshold V 0.2 V DD *Logic inputs meet typical CMOS I/O conditions for source/sink current (~1 A). Specifications subject to change without notice. D 2 REV.