Ultracompact, 1.5 A Thermoelectric Cooler (TEC) Controller Data Sheet ADN8834 FEATURES FUNCTIONAL BLOCK DIAGRAM VLIM/ Patented high efficiency single inductor architecture VDD SD ILIM VTEC ITEC PVIN Integrated low R MOSFETs for the TEC controller DSON TEC voltage and current operation monitoring ERROR AMP TEC DRIVER No external sense resistor required IN1P TEC CURRENT AND VOLTAGE Independent TEC heating and cooling current limit settings IN1N SENSE AND LIMIT LDR LINEAR Programmable maximum TEC voltage POWER OUT1 STAGE 2.0 MHz PWM driver switching frequency External synchronization COMP AMP Two integrated, zero drift, rail-to-rail chopper amplifiers IN2P CONTROLLER SW Capable of NTC or RTD thermal sensors IN2N PWM POWER 2.50 V reference output with 1% accuracy STAGE SFB OUT2 Temperature lock indicator Available in a 25-ball, 2.5 mm 2.5 mm WLCSP or in a VOLTAGE 24-lead, 4 mm 4 mm LFCSP OSCILLATOR REFERENCE APPLICATIONS TEC temperature control AGND VREF EN/SY PGNDx Optical modules Figure 1. Optical fiber amplifiers Optical networking systems Instruments requiring TEC temperature control GENERAL DESCRIPTION 1 The ADN8834 is a monolithic TEC controller with an integrated The temperature control loop of the ADN8834 is stabilized by TEC controller. It has a linear power stage, a pulse-width PID compensation utilizing the built in, zero drift chopper modulation (PWM) power stage, and two zero-drift, rail-to-rail amplifiers. The internal 2.50 V reference voltage provides a 1% accurate output that is used to bias a thermistor temperature operational amplifiers. The linear controller works with the PWM driver to control the internal power MOSFETs in an H-bridge sensing bridge as well as a voltage divider network to program configuration. By measuring the thermal sensor feedback the maximum TEC current and voltage limits for both the heating voltage and using the integrated operational amplifiers as a and cooling modes. With the zero drift chopper amplifiers, proportional integral differential (PID) compensator to condition extremely good long-term temperature stability is maintained via the signal, the ADN8834 drives current through a TEC to settle an autonomous analog temperature control loop. the temperature of a laser diode or a passive component attached Table 1. TEC Family Models to the TEC module to the programmed target temperature. Device No. MOSFET Thermal Loop Package The ADN8834 supports negative temperature coefficient (NTC) ADN8831 Discrete Digital/analog LFCSP (CP-32-7) thermistors as well as positive temperature coefficient (PTC) ADN8833 Integrated Digital WLCSP (CB-25-7), resistive temperature detectors (RTD). The target temperature is LFCSP (CP-24-15) set as an analog voltage input either from a digital-to-analog ADN8834 Integrated Digital/analog WLCSP (CB-25-7), converter (DAC) or from an external resistor divider. LFCSP (CP-24-15) 1 Product is covered by U.S. Patent No. 6,486,643. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20152018 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 12954-001ADN8834 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 TEC Voltage/Current Monitor ................................................. 16 Applications ....................................................................................... 1 Maximum TEC Voltage Limit .................................................. 16 Functional Block Diagram .............................................................. 1 Maximum TEC Current Limit ................................................. 17 General Description ......................................................................... 1 Applications Information .............................................................. 18 Revision History ............................................................................... 2 Signal Flow .................................................................................. 18 Specifications ..................................................................................... 3 Thermistor Setup ........................................................................ 18 Absolute Maximum Ratings ............................................................ 6 Thermistor Amplifier (Chopper 1) .......................................... 19 Thermal Resistance ...................................................................... 6 PID Compensation Amplifier (Chopper 2) ............................ 19 ESD Caution .................................................................................. 6 MOSFET Driver Amplifiers ...................................................... 20 Pin Configurations and Function Descriptions ........................... 7 PWM Output Filter Requirements .......................................... 20 Typical Performance Characteristics ............................................. 8 Input Capacitor Selection .......................................................... 21 Detailed Functional Block Diagram ............................................ 12 Power Dissipation....................................................................... 21 Theory of Operation ...................................................................... 13 PCB Layout Guidelines .................................................................. 23 Analog PID Control ................................................................... 14 Block Diagrams and Signal Flow ............................................. 23 Digital PID Control .................................................................... 14 Guidelines for Reducing Noise and Minimizing Power Loss .... 23 Powering the Controller ............................................................ 14 Example PCB Layout Using Two Layers ................................. 24 Enable and Shutdown ................................................................ 15 Outline Dimensions ....................................................................... 27 Oscillator Clock Frequency ....................................................... 15 Ordering Guide .......................................................................... 27 Temperature Lock Indicator (LFCSP Only) ........................... 15 Soft Start on Power-Up .............................................................. 15 REVISION HISTORY 9/18Rev. A to Rev. B Changes to Powering the Controller Section and Figure 27 Added Patent Information............................................................... 1 Caption ............................................................................................ 14 8/15Rev. 0 to Rev. A Change to Soft Start on Power-Up Section ................................. 15 Added 24-Lead LFCSP ....................................................... Universal Change to Figure 33 ....................................................................... 18 Changes to Features Section and Table 1 ...................................... 1 Changes to Table 7 .......................................................................... 21 Changes to Table 2 ............................................................................ 3 Added Table 8 Renumbered Sequentially .................................. 21 Changes to Table 3 ............................................................................ 6 Updated Outline Dimensions ....................................................... 27 Added Figure 3 Renumbered Sequentially .................................. 7 Changes to Ordering Guide .......................................................... 27 Changes to Figure 13 ........................................................................ 9 4/15Revision 0: Initial Version Changes to Figure 23 and Figure 24 ............................................. 11 Changes to Figure 25 ...................................................................... 12 Rev. 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