1 A, Low V , Low Noise,
IN
CMOS Linear Regulator
Data Sheet
ADP1761
FEATURES TYPICAL APPLICATION CIRCUITS
ADP1761
1 A maximum output current
V = 1.5V
V = 1.7V OUT
IN
VIN VOUT
Low input voltage supply range
C C
IN OUT
10F 10F
SENSE
V = 1.10 V to 1.98 V, no external bias supply required
IN
R
ON
PULL-UP
Fixed output voltage range: V = 0.9 V to 1.5 V EN
OUT_FIXED 100k
OFF
PG PG
Adjustable output voltage range: V = 0.5 V to 1.5 V
OUT_ADJ
SS VADJ
Ultralow noise: 2 V rms, 100 Hz to 100 kHz
C
SS VREG REFCAP
Noise spectral density 10nF
C
C
GND REF
REG
1F
1F
4 nV/Hz at 10 kHz
3 nV/Hz at 100 kHz
Figure 1. Fixed Output Operation
Low dropout voltage: 30 mV typical at 1 A load
ADP1761
V = 1.7V V = 1.5V
Operating supply current: 4.5 mA typical at no load IN OUT
VIN VOUT
C C
IN OUT
1.5% fixed output voltage accuracy over line, load, and
10F 10F
SENSE
temperature
R
PULL-UP ON
100k
EN
Excellent power supply rejection ratio (PSRR) performance
OFF
PG PG
SS
67 dB typical at 10 kHz at 1 A load
VADJ
51 dB typical at 100 kHz at 1 A load C
VREG REFCAP R
SS ADJ
10nF 10k
C
C REF
REG
Excellent load/line transient response GND
1F
1F
Soft start to reduce inrush current
Figure 2. Adjustable Output Operation
Optimized for small 10 F ceramic capacitors
Current-limit and thermal overload protection
Table 1. Related Devices
Power-good indicator
Input Maximum Fixed/
Precision enable
Device Package
Voltage Current Adjustable
16-lead, 3 mm 3 mm LFCSP package
ADP1762 1.10 V to 2 A Fixed/adjustable 16-lead
1.98 V LFCSP
APPLICATIONS
ADP1763 1.10 V to 3 A Fixed/adjustable 16-lead
Regulation to noise sensitive applications such as radio
1.98 V LFCSP
frequency (RF) transceivers, analog-to-digital converter
ADP1740/ 1.6 V to 2 A Fixed/adjustable 16-lead
(ADC) and digital-to-analog converter (DAC) circuits,
ADP1741 3.6 V LFCSP
phase-locked loops (PLLs), voltage controlled oscillators
ADP1752/ 1.6 V to 0.8 A Fixed/adjustable 16-lead
(VCOs) and clocking integrated circuits ADP1753 3.6 V LFCSP
Field-programmable gate array (FPGA) and digital signal
ADP1754/ 1.6 V to 1.2 A Fixed/adjustable 16-lead
ADP1755 3.6 V LFCSP
processor (DSP) supplies
Medical and healthcare
Industrial and instrumentation
The ADP1761 delivers optimal transient performance with
GENERAL DESCRIPTION
minimal board area.
The ADP1761 is a low noise, low dropout (LDO) linear regulator. It
The ADP1761 is available in fixed output voltages ranging from
is designed to operate from a single input supply with an input
0.9 V to 1.5 V. The output of the adjustable output model can be
voltage as low as 1.10 V, without the requirement of an external
set from 0.5 V to 1.5 V through an external resistor connected
bias supply to increase efficiency and provide up to 1 A of
output current. between VADJ and ground.
The low 30 mV typical dropout voltage at a 1 A load allows the The ADP1761 has an externally programmable soft start time by
ADP1761 to operate with a small headroom while maintaining connecting a capacitor to the SS pin. Short-circuit and thermal
overload protection circuits prevent damage in adverse conditions.
regulation and providing better efficiency. The ADP1761 is
The ADP1761 is available in a small 16-lead LFCSP package for the
optimized for stable operation with small 10 F ceramic output
smallest footprint solution to meet a variety of applications.
capacitors.
Rev. A Document Feedback
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12919-001
12919-002ADP1761 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1 Soft Start Function ..................................................................... 11
Applications ....................................................................................... 1 Adjustable Output Voltage ........................................................ 12
General Description ......................................................................... 1 Enable Feature ............................................................................ 12
Typical Application Circuits ............................................................ 1 Power-Good (PG) Feature ........................................................ 12
Revision History ............................................................................... 2 Applications Information .............................................................. 13
Specifications ..................................................................................... 3 Capacitor Selection .................................................................... 13
Input and Output Capacitor: Recommended Specifications . 4 Undervoltage Lockout ............................................................... 14
Absolute Maximum Ratings ............................................................ 5 Current-Limit and Thermal Overload Protection ................. 14
Thermal Data ................................................................................ 5 Thermal Considerations ............................................................ 14
Thermal Resistance ...................................................................... 5 PCB Layout Considerations ...................................................... 17
ESD Caution .................................................................................. 5 Outline Dimensions ....................................................................... 18
Pin Configuration and Function Descriptions ............................. 6 Ordering Guide .......................................................................... 18
Typical Performance Characteristics ............................................. 7
Theory of Operation ...................................................................... 11
REVISION HISTORY
9/2016Rev. 0 to Rev. A
Changes to Figure 23 and Figure 24 ............................................. 11
4/2016Revision 0: Initial Version
Rev. A | Page 2 of 18