Synchronous Buck Controller with Constant On-Time and Valley Current Mode Data Sheet ADP1874/ADP1875 FEATURES TYPICAL APPLICATIONS CIRCUIT V = 2.95V TO 20V IN Power input voltage range: 2.95 V to 20 V On-board bias regulator VIN Minimum output voltage: 0.6 V C C ADP1874/ C C IN C2 0.6 V reference voltage with 1.0% accuracy R ADP1875 C COMP BST Supports all N-channel MOSFET power stages C Q1 10k BST L VREG EN DRVH Available in 300 kHz, 600 kHz, and 1.0 MHz options V R TOP OUT V OUT FB No current-sense resistor required C SW OUT R BOT LOAD Q2 Power saving mode (PSM) for light loads (ADP1875 only) GND DRVL C VREG2 Resistor programmable current limit R PGD VREG PGOOD V C EXT VREG Power good with internal pull-up resistor VREG IN SS C SS Externally programmable soft start RES R R TRK2 RES TRACK V MASTER Thermal overload protection R PGND TRK1 Short-circuit protection Standalone precision enable input Figure 1. Typical Applications Circuit Integrated bootstrap diode for high-side drive Starts into a precharged output 100 Available in a 16-lead QSOP package V = 5V (PSM) 95 IN 90 APPLICATIONS 85 80 Telecom and networking systems 75 Mid- to high-end servers 70 V = 16.5V IN Set-top boxes 65 V = 13V DSP core power supplies 60 IN V = 13V (PSM) 55 IN GENERAL DESCRIPTION T = 25C 50 A V = 1.8V OUT 45 f = 300kHz The ADP1874/ADP1875 are versatile current mode, synchronous SW V = 16.5V (PSM) 40 IN WRTH INDUCTOR: step-down controllers. They provide superior transient response, 35 744325120, L = 1.2H, DCR = 1.8m INFINEON FETs: optimal stability, and current-limit protection by using a constant 30 BSC042N03MS G (UPPER/LOWER) 25 on-time, pseudo fixed frequency with a programmable current 10 100 1k 10k 100k limit, current control scheme. In addition, these devices offer LOAD CURRENT (mA) optimum performance at low duty cycles by using a valley, current Figure 2. ADP1874/ADP1875 Efficiency vs. Load Current (V = 1.8 V, 300 kHz) OUT mode control architecture. This allows the ADP1874/ADP1875 In addition, soft start programmability is included to limit input to drive all N-channel power stages to regulate output voltages in-rush current from the input supply during startup and to to as low as 0.6 V. provide reverse current protection during precharged output The ADP1875 is the power saving mode (PSM) version of conditions. The low-side current sense, current gain scheme, and the device and is capable of pulse skipping to maintain output integration of a boost diode, along with the PSM/forced pulse- regulation while achieving improved system efficiency at light width modulation (PWM) option, reduce the external part count loads (see the ADP1875 Power Saving Mode (PSM) section for and improve efficiency. more information). The ADP1874/ADP1875 operate over the 40C to +125C Available in three frequency options (300 kHz, 600 kHz, and junction temperature range and are available in a 16-lead QSOP 1.0 MHz, plus the PSM option), the ADP1874/ADP1875 are well package. suited for a wide range of applications that require a single-input power supply range from 2.95 V to 20 V. Low voltage biasing is supplied via a 5 V internal low dropout regulator (LDO). Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 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EFFICIENCY (%) 09347-001 09347-102ADP1874/ADP1875 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Timer Operation ........................................................................ 23 Applications ....................................................................................... 1 Pseudo-Fixed Frequency ........................................................... 24 General Description ......................................................................... 1 Power Good Monitoring ........................................................... 24 Typical Applications Circuit ............................................................ 1 Voltage Tracking ......................................................................... 25 Revision History ............................................................................... 2 Applications Information .............................................................. 27 Specifications ..................................................................................... 3 Feedback Resistor Divider ........................................................ 27 Absolute Maximum Ratings ............................................................ 6 Inductor Selection ...................................................................... 27 Thermal Resistance ...................................................................... 6 Output Ripple Voltage (V ) .................................................. 27 RR Boundary Condition .................................................................... 6 Output Capacitor Selection....................................................... 27 ESD Caution .................................................................................. 6 Compensation Network ............................................................ 28 Pin Configuration and Function Descriptions ............................. 7 Efficiency Consideration ........................................................... 29 Typical Performance Characteristics ............................................. 8 Input Capacitor Selection .......................................................... 30 ADP1874/ADP1875 Block Digram ............................................... 18 Thermal Considerations ............................................................ 31 Theory of Operation ...................................................................... 19 Design Example .......................................................................... 32 Startup .......................................................................................... 19 External Component Recommendations .................................... 34 Soft Start ...................................................................................... 19 Layout Considerations ................................................................... 36 Precision Enable Circuitry ........................................................ 19 IC Section (Left Side of Evaluation Board) ............................. 38 Undervoltage Lockout ............................................................... 19 Power Section ............................................................................. 38 On-Board Low Dropout Regulator .......................................... 20 Differential Sensing .................................................................... 39 Thermal Shutdown ..................................................................... 20 Typical Application Circuits ......................................................... 40 Programming Resistor (RES) Detect Circuit .......................... 20 12 A, 300 kHz High Current Application Circuit .................. 40 Valley Current-Limit Setting .................................................... 20 5.5 V Input, 600 kHz Application Circuit ............................... 40 Hiccup Mode During Short Circuit ......................................... 22 300 kHz High Current Application Circuit ............................ 41 Synchronous Rectifier ................................................................ 22 Outline Dimensions ....................................................................... 42 ADP1875 Power Saving Mode (PSM) ...................................... 22 Ordering Guide .......................................................................... 42 REVISION HISTORY 7/12Rev. 0 to Rev. A Changes to Table 7 .......................................................................... 21 3/11Revision 0: Initial Version Rev. A Page 2 of 44