5.5 V, 5 A/6 A, High Efficiency, Step-Down DC-to-DC Regulators with Output Tracking Data Sheet ADP2165/ADP2166 FEATURES TYPICAL APPLICATION CIRCUIT Continuous output current ADP2165/ ADP2165: 5 A ADP2166 PVIN BST V PVIN C ADP2166: 6 A BST L1 AVIN C IN SW V OUT EN Integrated MOSFET C OUT PGOOD R High-side on resistance: 19 m TOP SYNC R Low-side on resistance: 15 m RT FB RT COMP Reference voltage: 0.6 V 1% over temperature range TRK C VREG C R CP C Input voltage range: 2.7 V to 5.5 V R BOT VREG SS C C Current mode architecture GND PGND C SS Switching frequency Fixed frequency: 620 kHz or 1.2 MHz Figure 1. Adjustable frequency: 250 kHz to 1.4 MHz Synchronizes to external clock: 250 kHz to 1.4 MHz The ADP2165/ADP2166 are designed to be extremely flexible Selectable synchronize phase shift: in phase or out of phase with the addition of a minimal amount of external components External compensation to program soft start and control loop compensation. Programmable soft start The ADP2165/ADP2166 are supplied from an input voltage of Startup into a precharged output 2.7 V to 5.5 V. Output voltage options include 3.3 V, 2.5 V, 1.8 V, Voltage tracking input 1.5 V, 1.2 V, or 1.0 V fixed outputs and adjustable options capable Power-good output and precision enable input of supporting an output voltage range from 0.6 V to 90% of the Accurate current limit input voltage. Protection features include undervoltage lockout Available in 24-lead, 4 mm 4 mm LFCSP package (UVLO), overvoltage protection (OVP), overcurrent protection Supported by ADIsimPower design tool (OCP), and thermal shutdown (TSD) for robust performance. APPLICATIONS The ADP2165/ADP2166 operate over the 40C to +125C Point of load regulation junction temperature range and are available in a 24-lead Communications and networking LFCSP package. High end consumer Industrial, instrumentation, and healthcare 100 V = 3.3V PVIN GENERAL DESCRIPTION 95 The ADP2165/ADP2166 are high efficiency, current mode 90 V = 5V PVIN control, step-down dc-to-dc regulators with an integrated 19 m 85 high-side FET and a 15 m synchronous rectified FET. The 80 ADP2165/ADP2166 combine a small size, 4 mm 4 mm LFCSP 75 package with an accurate current limit, resulting in a smaller 70 inductor size and a high power density, point of load solution. 65 Key features include precision enable, power-good monitor, 60 and output voltage tracking to facilitate robust sequencing. The switching frequency can be programmed from 250 kHz 55 V = 1.8V OUT f = 600kHz SW to 1.4 MHz, or it can be fixed at 620 kHz or 1.2 MHz. The 50 0 1 2 3 4 5 6 synchronization function allows the switching frequency to OUTPUT CURRENT (A) synchronize to an external clock, minimizing the Figure 2. Efficiency vs. Output Current electromagnetic interference (EMI) of the system. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20142017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com EFFICIENCY (%) 10956-002 10956-001ADP2165/ADP2166 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Undervoltage Lockout ............................................................... 13 Applications ....................................................................................... 1 Thermal Shutdown .................................................................... 13 General Description ......................................................................... 1 Applications Information .............................................................. 14 Typical Application Circuit ............................................................. 1 ADIsimPower Design Tool ....................................................... 14 Revision History ............................................................................... 2 Input Capacitor Selection .......................................................... 14 Functional Block Diagram .............................................................. 3 Output Voltage Setting .............................................................. 14 Specifications ..................................................................................... 4 Voltage Conversion Limitations ............................................... 14 Absolute Maximum Ratings ............................................................ 6 Inductor Selection ...................................................................... 15 Thermal Resistance ...................................................................... 6 Output Capacitor Selection....................................................... 15 ESD Caution .................................................................................. 6 Compensation Design ............................................................... 16 Pin Configuration and Function Descriptions ............................. 7 Design Example .............................................................................. 17 Typical Performance Characteristics ............................................. 8 Output Voltage Setting .............................................................. 17 Theory of Operation ...................................................................... 12 Frequency Setting ....................................................................... 17 Control Scheme .......................................................................... 12 Inductor Selection ...................................................................... 17 PWM Mode ................................................................................. 12 Output Capacitor Selection....................................................... 18 Enable/Shutdown ....................................................................... 12 Compensation Components ..................................................... 18 Internal Regulator (VREG) ....................................................... 12 Soft Start Time Program ........................................................... 18 Bootstrap Circuitry .................................................................... 12 Input Capacitor Selection .......................................................... 18 Oscillator and Synchronization ................................................ 12 Recommended External Components .................................... 19 Soft Start ...................................................................................... 13 Printed Circuit Board Layout Recommendations ..................... 20 Tracking ....................................................................................... 13 Reference Designs .......................................................................... 21 Power-Good (PGOOD) ............................................................. 13 Outline Dimensions ....................................................................... 23 Peak Current-Limit and Short-Circuit Protection ................. 13 Ordering Guide .......................................................................... 23 Overvoltage Protection .............................................................. 13 REVISION HISTORY 8/2017Rev. A to Rev. B Changed LFCSP WQ to LFCSP .......................................... Throughout Updated Outline Dimensions ................................................................. 23 Changes to Ordering Guide ..................................................................... 23 9/2016Rev. 0 to Rev. A Change to Compensation Components Section ........................ 18 Change to Table 8 ........................................................................... 19 8/2014Revision 0: Initial Version Rev. B Page 2 of 23