Power Management Unit for Imaging Modules Data Sheet ADP5020 FEATURES TYPICAL APPLICATIONS CIRCUIT V IN Input voltage range: 2.4 V to 5.5 V 2.4V TO 5.5V SW1 VDD1 Low standby current: 1 A 10F 2.2H Switching frequency: 3 MHz 2 V OUT1 I C interface VDD2 VOUT1 2.5V TO 3.7V Synchronous Buck 1 regulator: 600 mA VOUT1 10F Synchronous Buck 2 regulator: 250 mA VDD3 PGND1 Low dropout regulator (LDO): 150 mA V OUT2 ADP5020 2.2H Internal compensation 1.1V TO 1.8V VDDA SW2 Internal soft start 1F 4.7F V VOUT2 DD IO Thermal shutdown 1.7V TO 3.6V VDD IO PGND2 20-lead 4 mm 4 mm LFCSP V OUT3 10k 10k 0.1F 1.8V TO 3.3V APPLICATIONS VOUT3 1F SDA Digital cameras, handsets SCL Mobile TVs EXT. FREQ SYNC XSHTDN 9.6/19.2MHz EN/GPIO DGND AGND Figure 1. GENERAL DESCRIPTION The ADP5020 provides a highly integrated power solution that The ADP5020 provides high performance, reduces component includes all of the power circuits necessary for a digital imaging count and size, and is lower in cost when compared to conven- module. It comprises two step-down dc-to-dc converters, one tional designs. LDO, and a power sequence controller. All dc-to-dc converters The ADP5020 runs on input voltage from 2.4 V to 5.5 V and integrate power pMOSFETs and nMOSFETs, making the system supports one-cell lithium-ion (Li+) batteries. The high perfor- simpler and more compact and reducing the cost. The ADP5020 mance LDO maximizes noise suppression. The ADP5020 can be has digitally programmed output voltages and buck converters 2 activated via an I C interface or through a dedicated enable input. that can source up to 600 mA. A fixed frequency operation of During logic-controlled shutdown, the input is disconnected 3 MHz enables the use of tiny inductors and capacitors. The buck from the output source, and the part draws 1 A typical from converters use a voltage mode, constant-frequency PWM control the input source. Other key features include undervoltage lockout scheme, and the synchronous rectification is implemented to to prevent deep-battery discharge and soft start to prevent input reduce the power loss. The Buck 1 regulator operates at up to current overshoot at startup. The ADP5020 is available in a 93% efficiency. 20-lead LFCSP. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20092018 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 07774-001ADP5020 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Undervoltage Lockout ............................................................... 13 Applications ....................................................................................... 1 Thermal Shutdown .................................................................... 13 Typical Applications Circuit ............................................................ 1 Control Registers ............................................................................ 14 General Description ......................................................................... 1 Device Address ........................................................................... 14 Revision History ............................................................................... 2 Register Map ............................................................................... 14 Functional Block Diagram .............................................................. 3 Register Descriptions ................................................................. 14 Specifications ..................................................................................... 4 Power-Up/Power-Down Sequence ............................................... 17 Switching Specifications .............................................................. 5 Sequencer .................................................................................... 17 DC-to-DC Conversion Specifications, Buck 1 Regulator ....... 5 Default Power-On Sequence with EN Pin .............................. 17 2 DC-to-DC Conversion Specifications, Buck 2 Regulator ....... 6 Power-On Sequence Using the I C Interface .............................. 19 VOUT3 Specifications, Low Dropout (LDO) Regulator ........ 6 Power-Up/Power-Down State Flow ......................................... 20 2 I C Timing Specifications ............................................................ 7 Applications Information .............................................................. 21 Absolute Maximum Ratings ............................................................ 8 Power Good Status ..................................................................... 21 Thermal Resistance ...................................................................... 8 XSHTDN Logic .......................................................................... 21 ESD Caution .................................................................................. 8 Components Selection ............................................................... 21 Pin Configurations and Function Descriptions ........................... 9 LDO Input Filter ......................................................................... 22 Typical Performance Characteristics ........................................... 10 Layout Recommendations ............................................................. 23 Theory of Operation ...................................................................... 13 Applications Schematic ............................................................. 23 Circuit Operation ....................................................................... 13 PCB Board Layout Recommendations .................................... 24 Internal Compensation .............................................................. 13 External Component List .......................................................... 24 Current Limiting and Short-Circuit Protection ..................... 13 Outline Dimensions ....................................................................... 25 Synchronization .......................................................................... 13 Ordering Guide .......................................................................... 25 2 I C Interface ................................................................................ 13 REVISION HISTORY 9/2018Rev. 0 to Rev. A Changed CP-20-4 to CP-20-10 .................................... Throughout Changes to Table 8 ............................................................................ 8 Changes to Figure 4 and Figure 5 ................................................... 9 Updated Outline Dimensions ....................................................... 25 Changes to Ordering Guide .......................................................... 25 4/2009Revision 0: Initial Version Rev. A Page 2 of 28