Dual 3 MHz, 1200 mA Buck Regulators with One 300 mA LDO Data Sheet ADP5024 a predefined threshold. When the load current falls below a pre- FEATURES defined threshold, the regulator operates in power save mode Main input voltage range: 2.3 V to 5.5 V (PSM), improving the light load efficiency. Two 1200 mA buck regulators and one 300 mA LDO 24-lead, 4 mm 4 mm LFCSP package Table 1. Family Models Regulator accuracy: 1.8% Maximum Factory programmable or external adjustable VOUTx Model Channels Current Package 3 MHz buck operation with forced PWM and automatic ADP5023 2 Buck, 1 LDO 800 mA, LFCSP (CP-24-10) 300 mA PWM/PSM modes ADP5024 2 Buck, 1 LDO 1.2 A, LFCSP (CP-24-10) BUCK1/BUCK2: output voltage range from 0.8 V to 3.8 V 300 mA LDO: output voltage range from 0.8 V to 5.2 V ADP5034 2 Buck, 2 LDOs 1.2 A, LFCSP (CP-24-10), LDO: input supply voltage from 1.7 V to 5.5 V 300 mA TSSOP (RE-28-1) LDO: high PSRR and low output noise ADP5037 2 Buck, 2 LDOs 800 mA, LFCSP (CP-24-10) 300 mA APPLICATIONS ADP5033 2 Buck, 2 LDOs 800 mA, WLCSP (CB-16-8) with 2 EN pins 300 mA Power for processors, ASICS, FPGAs, and RF chipsets Portable instrumentation and medical devices The two bucks operate out of phase to reduce the input capacitor Space constrained devices requirement. The low quiescent current, low dropout voltage, and wide input voltage range of the LDO extends the battery life of GENERAL DESCRIPTION portable devices. The ADP5024 LDO maintains power supply The ADP5024 combines two high performance buck regula- rejection greater than 60 dB for frequencies as high as 10 kHz tors and one low dropout (LDO) regulator in a small, 24-lead, while operating with a low headroom voltage. 4 mm 4 mm LFCSP to meet demanding performance and Regulators in the ADP5024 are activated though dedicated board space requirements. enable pins. The default output voltages can be either externally The high switching frequency of the buck regulators enables tiny set in the adjustable version or factory programmable to a wide multilayer external components and minimizes the board space. range of preset values in the fixed voltage version. When the MODE pin is set high, the buck regulators operate in forced PWM mode. When the MODE pin is set low, the buck regulators operate in PWM mode when the load current is above TYPICAL APPLICATION CIRCUIT AVIN HOUSEKEEPING C AVIN VOUT1 0.1F L1 1H VIN1 SW1 2.3V TO V AT OUT1 5.5V C1 1200mA R1 FB1 4.7F BUCK1 C5 R2 10F PGND1 ON EN1 EN1 OFF MODE PWM MODE PSM/PWM VOUT2 VIN2 MODE L2 1H SW2 C2 V AT OUT2 4.7F 1200mA BUCK2 R3 FB2 C6 EN2 R4 10F EN2 PGND2 ON OFF EN3 VOUT3 V AT OUT3 EN3 LDO 300mA FB3 R5 VIN3 (ANALOG) 1.7V TO C7 5.5V C3 1F R6 1F ADP5024 AGND Figure 1. Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20112013 Analog Devices, Inc. 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Technical Support www.analog.com 09888-001ADP5024 Data Sheet TABLE OF CONTENTS Features .....................................................................................1 Theory of Operation................................................................ 16 Applications...............................................................................1 Power Management Unit ..................................................... 17 General Description ..................................................................1 BUCK1 and BUCK2 ............................................................ 19 Typical Application Circuit........................................................1 LDO..................................................................................... 20 Revision History ........................................................................2 Applications Information ........................................................ 21 Specifications .............................................................................3 Buck External Component Selection ................................... 21 General Specifications............................................................3 LDO External Component Selection ................................... 23 BUCK1 and BUCK2 Specifications........................................4 Power Dissipation and Thermal Considerations ..................... 24 LDO Specifications ................................................................5 Buck Regulator Power Dissipation....................................... 24 Input and Output Capacitor, Recommended Specifications ..6 Junction Temperature .......................................................... 25 Absolute Maximum Ratings ......................................................7 PCB Layout Guidelines............................................................ 26 Thermal Resistance ................................................................7 Typical Application Schematics ............................................... 27 ESD Caution ..........................................................................7 Bill of Materials.................................................................... 27 Pin Configuration and Function Descriptions...........................8 Outline Dimensions ................................................................ 28 Typical Performance Characteristics .........................................9 Ordering Guide ................................................................... 28 REVISION HISTORY 5/13Rev. D to Rev. E Changes to Figure 6, Figure 7 and Figure 8................................ 9 Changes to Figure 30 and Figure 31 ........................................ 13 Added Table 1 Renumbered Sequentially .................................1 Changes to Figure 34 ............................................................... 14 Changes to Figure 1 ...................................................................1 Change to Figure 38 ................................................................ 14 Changes to NC Pin Description.................................................8 Changes to Undervoltage Lockout Section .............................. 17 Changes to Figure 48 ...............................................................20 Changes to Buck Regulator Power Dissipation Section ........... 24 Changes to Figure 50 ...............................................................22 Changes to Figure 52 and Figure 53.........................................27 1/12Rev. 0 to Rev. A 1/13Rev. C to Rev. D Changes to Features Section and Figure 1 ................................. 1 Changes to Table 2..................................................................... 4 Changes to Figure 9 .................................................................10 Changes to Table 3..................................................................... 5 Changes to Ordering Guide .....................................................28 Changes to Table 4..................................................................... 6 12/12Rev. B to Rev. C Changes to Table 7..................................................................... 8 Changes to Ordering Guide .....................................................28 Changes to Figure 34 ............................................................... 14 Changes to LDO Section and Figure 48................................... 20 11/12Rev. A to Rev. B Changes to Table 9 and Figure 50 ............................................ 22 Changes to Features Section ......................................................1 Changes to Buck Regulator Power Dissipation Section ........... 24 Changes to Output Voltage Accuracy and Voltage Feedback Changes to Figure 52 and Figure 53 ........................................ 27 Parameters, Table 2 ....................................................................4 8/11Revision 0: Initial Version Changes to Output Voltage Accuracy and Voltage Feedback Parameters, Table 3 ....................................................................5 Rev. E Page 2 of 28