Dual 3 MHz, 800 mA Buck Regulators with Two 300 mA LDOs Data Sheet ADP5033 FEATURES TYPICAL APPLICATION CIRCUIT ADP5033 Main input voltage range: 2.3 V to 5.5 V L1 1H VOUT1 Two 800 mA buck regulators and two 300 mA LDOs SW1 2.3V VIN1 TO VOUT1 800mA Tiny, 16-ball, 2 mm 2 mm WLCSP package C1 5.5V BUCK1 C5 4.7F Regulator accuracy: 1.8% PGND1 10F EN1 ENA MODE Factory programmable VOUTx ON EN2 3 MHz buck operation with forced PWM and auto PWM/PSM OFF ENB EN3 PWM MODE EN4 PSM/PWM modes VIN2 BUCK1/BUCK2: output voltage range from 0.8 V to 3.8 V MODE L2 1H VOUT2 SW2 C2 4.7F LDO1/LDO2: output voltage range from 0.8 V to 5.2 V 800mA VOUT2 BUCK2 C6 LDO1/LDO2: low input supply voltage from 1.7 V to 5.5 V 10F EN2 PGND2 LDO1/LDO2: high PSRR and low output noise EN3 VOUT3 1.7V VIN3 VOUT3 LDO1 APPLICATIONS TO C3 (ANALOG) 300mA 5.5V 1F C7 Power for processors, ASICS, FPGAs, and RF chipsets 1F EN4 Portable instrumentation and medical devices VOUT4 VOUT4 VIN4 LDO2 C4 Space constrained devices 300mA (DIGITAL) 1F C8 1F AGND Figure 1. GENERAL DESCRIPTION The ADP5033 combines two high performance buck regulators The regulators in the ADP5033 are activated by the ENA and ENB and two low dropout regulators (LDO) in a tiny, 16-ball, 2 mm pins. The specific channels controlled by ENA and ENB are set 2 mm WLCSP to meet demanding performance and board space by factory programming. A high voltage level applied to the enable requirements. pins activates the regulators. The default output voltages are factory programmable and can be set to a wide range of options. The high switching frequency of the buck regulators enables tiny multilayer external components and minimizes the board space. Table 1. Family Models When the MODE pin is set high, the buck regulators operate in Maximum forced PWM mode. When the MODE pin is set low, the buck Model Channels Current Package regulators operate in PWM mode when the load current is above ADP5023 2 Bucks, 1 LDO 800 mA, 300 mA LFCSP (CP-24-10) a predefined threshold. When the load current falls below a ADP5024 2 Bucks, 1 LDO 1.2 A, 300 mA LFCSP (CP-24-10) ADP5034 2 Bucks, 2 LDOs 1.2 A, 300 mA LFCSP (CP-24-10), predefined threshold, the regulator operates in power save TSSOP (RE-28-1) mode (PSM), improving the light load efficiency. ADP5037 2 Bucks, 2 LDOs 800 mA, 300 mA LFCSP (CP-24-10) The two bucks operate out of phase to reduce the input capacitor ADP5033 2 Bucks, 2 LDOs with 800 mA, 300 mA WLCSP (CB-16-8) 2 EN pins requirement and noise. ADP5040 1 Buck, 2 LDOs 1.2 A, 300 mA LFCSP (CP-20-10) The low quiescent current, low dropout voltage, and wide input ADP5041 1 Buck, 2 LDOs with 1.2 A, 300 mA LFCSP (CP-20-10) voltage range of the ADP5033 LDO extend the battery life of Supervisory, Watchdog, Manual Reset portable devices. The ADP5033 LDOs maintain power supply ADP5133 2 Bucks with 2 ENx pins 800 mA WLCSP (CB-16-8) rejection greater than 60 dB for frequencies as high as 10 kHz ADP5134 2 Bucks, 2 LDOs with 1.2 A, 300 mA LFCSP (CP-24-10) while operating with a low headroom voltage. precision enable and power-good output Rev. G Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20112014 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com ACTIV. AND UVLO 09788-001ADP5033 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 15 Applications ....................................................................................... 1 Power Management Unit ........................................................... 15 Typical Application Circuit ............................................................. 1 BUCK1 and BUCK2 .................................................................. 16 General Description ......................................................................... 1 LDO1 and LDO2 ........................................................................ 17 Revision History ............................................................................... 2 Applications Information .............................................................. 18 Specif icat ions ..................................................................................... 3 Buck External Component Selection ....................................... 18 General Specifications ................................................................. 3 LDO Capacitor Selection .......................................................... 20 BUCK1 and BUCK2 Specifications ........................................... 4 Power Dissipation and Thermal Considerations ....................... 21 LDO1 and LDO2 Specifications ................................................. 4 Buck Regulator Power Dissipation .......................................... 21 Input and Output Capacitor, Recommended Specifications ........ 5 Junction Temperature ................................................................ 22 Absolute Maximum Ratings ............................................................ 6 PCB Layout Guidelines .................................................................. 23 Thermal Resistance ...................................................................... 6 Typical Application Schematic ..................................................... 24 ESD Caution .................................................................................. 6 Outline Dimensions ....................................................................... 25 Pin Configuration and Function Descriptions ............................. 7 Ordering Guide .......................................................................... 26 Typical Performance Characteristics ............................................. 8 REVISION HISTORY 9/14Rev. F to Rev. G Moved Power Dissipation and Thermal Considerations Section .... 21 Changes to Page Layout ................................................................... 1 Changes to Buck Regulator Power Dissipation Section ............ 21 Changes to Table 1 ............................................................................ 1 Updated Outline Dimensions ....................................................... 25 Changes to Ordering Guide .......................................................... 26 Changes to Ordering Guide .......................................................... 25 10/13Rev. E to Rev. F 1/12Rev. 0 to Rev. A Changes to VIN1 Undervoltage Lockout Parameter, Table 2 ..... 3 Changes to Features Section and General Description Section .... 1 Changes to Undervoltage Lockout Section ................................. 16 Changes to Output Characteristics Parameter, Table 2 ................ 4 Changes to Output Characteristics Parameter, Table 3 and Moved Ordering Guide .................................................................. 26 Changes to Ordering Guide .......................................................... 26 Dropout Voltage Parameter, Table 3 ............................................... 4 Changes to Nominal Input and Output Capacitor Ratings 9/13Rev. D to Rev. E Parameter, Table 4 ............................................................................. 5 Changes to Table 1 ............................................................................ 1 Changes to Table 5 ............................................................................. 6 Changes to Ordering Guide .......................................................... 25 Changed V = V = V = V = 5.0 V to V = V = V = IN1 IN2 IN3 IN4 IN1 IN2 IN3 V = 3.6 V ......................................................................................... 8 IN4 5/13Rev. C to Rev. D Changes to Figure 4 to Figure 8 ....................................................... 8 Added Table 1 Renumbered Sequentially .................................... 1 Change to Figure 15 Caption and Figure 17 Caption ................ 10 Changes to Ordering Guide .......................................................... 25 Changes Figure 19 and Figure 20 ................................................. 10 Changes to Figure 31 and Figure 32............................................. 12 1/13Rev. B to Rev. C Changes to Figure 33, Figure 37, and Figure 38 ......................... 13 Changes to Figure 9 .......................................................................... 9 Changes to Buck Regulator Power Dissipation Section ............ 15 Changes to Ordering Guide .......................................................... 25 Changes to LDO Regulator Power Dissipation Section and Junction Temperature Section ...................................................... 16 10/12Rev. A to Rev. B Changes to Undervoltage Lockout Section ................................. 18 Changes to Features Section............................................................ 1 Changes to LDO1 and LDO2 Section ......................................... 19 Changes to Buck Output Voltage Accuracy Parameter, Table 2 ....... 4 Changes to Output Capacitor Section ......................................... 20 Changes to LDO Output Voltage Accuracy Parameter, Table 3 ....... 4 Changes to Table 9 .......................................................................... 21 Changes to Figure 6 to Figure 8 ...................................................... 8 Change to Input and Output Capacitor Properties Section ..... 22 Changes to Figure 30 to Figure 32 ................................................ 12 Changes to Ordering Guide .......................................................... 25 Changes to Figure 36 Caption ....................................................... 13 Changes to Undervoltage Lockout Section ................................. 16 5/11Revision 0: Initial Version Rev. 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