X-On Electronics has gained recognition as a prominent supplier of ADP5051ACPZ-R7 Power Management Specialised - PMIC across the USA, India, Europe, Australia, and various other global locations. ADP5051ACPZ-R7 Power Management Specialised - PMIC are a product manufactured by Analog Devices. We provide cost-effective solutions for Power Management Specialised - PMIC, ensuring timely deliveries around the world.

ADP5051ACPZ-R7 Analog Devices

ADP5051ACPZ-R7 electronic component of Analog Devices
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Part No.ADP5051ACPZ-R7
Manufacturer: Analog Devices
Category: Power Management Specialised - PMIC
Description: Power Management Specialised - PMIC Adj 12V uPMU 4Buck+POR/WDI+I2C I/F
Datasheet: ADP5051ACPZ-R7 Datasheet (PDF)
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



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1: USD 10.3391 ea
Line Total: USD 10.34 
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MOQ: 1  Multiples: 1
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Ship by Mon. 02 Dec to Fri. 06 Dec
MOQ : 1
Multiples : 1
1 : USD 17.0693
10 : USD 14.8691
25 : USD 14.1769
100 : USD 12.3098
250 : USD 11.7566

0
Ship by Thu. 28 Nov to Mon. 02 Dec
MOQ : 1
Multiples : 1
1 : USD 15.8834
10 : USD 14.296
25 : USD 13.8655
100 : USD 11.9429
250 : USD 11.4847
500 : USD 10.9082

   
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Integrated Power Solution with Quad Buck 2 Regulators, Supervisory Circuit, and I C Interface Data Sheet ADP5051 FEATURES TYPICAL APPLICATION CIRCUIT ADP5051 Wide input voltage range: 4.5 V to 15.0 V SYNC/MODE VREG INT VREG VDD OSCILLATOR RT C1 100mA 1.5% output accuracy over full temperature range C0 FB1 250 kHz to 1.4 MHz adjustable switching frequency PVIN1 4.5V TO 15V BST1 2 Adjustable/fixed output options via factory fuse or I C interface SW1 CHANNEL 1 C3 L1 VOUT1 C2 BUCK 2 COMP1 I C interface with interrupt on fault conditions (4A) VREG C4 EN1 Q1 Power regulation DL1 SS12 R ILIM1 Channel 1 and Channel 2: programmable 1.2 A/2.5 A/4 A PGND R ILIM2 sync buck regulators with low-side FET driver DL2 Q2 Channel 3 and Channel 4: 1.2 A sync buck regulators PVIN2 C5 CHANNEL 2 VREG VOUT2 SW2 BUCK COMP2 L2 Single 8 A output (Channel 1 and Channel 2 in parallel) (4A) C6 C7 BST2 EN2 Dynamic voltage scaling (DVS) for Channel 1 and Channel 4 FB2 Precision enable with 0.8 V accurate threshold PVIN3 BST3 Active output discharge switch C9 C8 L3 VOUT3 SW3 COMP3 CHANNEL 3 Programmable phase shift in 90 steps BUCK C10 (1.2A) FB3 EN3 Individual channel FPWM/PSM selection PGND3 SS34 Frequency synchronization input or output BST4 Optional latch-off protection on OVP/OCP failure PVIN4 C12 L4 VOUT4 SW4 CHANNEL 4 C11 Power-good flag on selected channels BUCK COMP4 C13 (1.2A) FB4 Low input voltage detection EN4 VREG PGND4 Open-drain processor reset with external adjustable threshold WDI RSTO WATCHDOG AND MR monitoring VTH RESET VOUTx Watchdog refresh input VDDIO PWRGD 2 I C ALERT SCL Manual reset input INT SDA Overheat detection on junction temperature EXPOSED PAD UVLO, OCP, and TSD protection Figure 1. APPLICATIONS Combining Channel 1 and Channel 2 in a parallel configuration provides a single output with up to 8 A of current. Channel 3 and Small cell base stations Channel 4 integrate both high-side and low-side MOSFETs to FPGA and processor applications deliver an output current of 1.2 A. Security and surveillance Medical applications The ADP5051 supervisory circuits monitor the voltage level. The watchdog timer generates a reset when the WDI pin does GENERAL DESCRIPTION not toggle within a preset timeout period. Select manual reset The ADP5051 combines four high performance buck regulators functionality via the processor reset mode or system power on/off and a supervisory circuit with a voltage monitor, a watchdog switch mode. function, and a manual reset in a 48-lead LFCSP package that 2 The optional I C interface offers flexible configurations, including meets demanding performance and board space requirements. adjustable and fixed output voltage, junction temperature overheat The device enables direct connection to high input voltages up to warning, low input voltage detection, and dynamic voltage scaling. 15.0 V with no preregulators. Table 1. Family Models Channel 1 and Channel 2 integrate high-side power MOSFET and 2 Model Channels I C Package low-side MOSFET drivers. In low-side power devices, use external ADP5050 Four bucks, one LDO Yes 48-Lead LFCSP NFETs to achieve an efficiency optimized solution and deliver a ADP5051 Four bucks, supervisory Yes 48-Lead LFCSP programmable output current of 1.2 A, 2.5 A, or 4 A. ADP5052 Four bucks, one LDO No 48-Lead LFCSP ADP5053 Four bucks, supervisory No 48-Lead LFCSP ADP5054 Four high current bucks No 48-Lead LFCSP Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20132016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 11635-001ADP5051 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Supervisory Circuit .................................................................... 26 2 Applications ....................................................................................... 1 I C Interface .................................................................................... 29 General Description ......................................................................... 1 SDA and SCL Pins ...................................................................... 29 2 Typical Application Circuit ............................................................. 1 I C Addresses .............................................................................. 29 Revision History ............................................................................... 3 Self-Clear Register Bits .............................................................. 29 2 Functional Block Diagram .............................................................. 4 I C Interface Timing Diagrams ................................................ 30 Specifications ..................................................................................... 5 Applications Information .............................................................. 31 Buck Regulator Specifications .................................................... 6 ADIsimPower Design Tool ....................................................... 31 Supervisory Specifications .......................................................... 8 Programming the Adjustable Output Voltage ........................ 31 2 I C Interface Timing Specifications ........................................... 9 Voltage Conversion Limitations ............................................... 31 Absolute Maximum Ratings .......................................................... 10 Current-Limit Setting ................................................................ 31 Thermal Resistance .................................................................... 10 Soft Start Setting ......................................................................... 32 ESD Caution ................................................................................ 10 Inductor Selection ...................................................................... 32 Pin Configuration and Function Descriptions ........................... 11 Output Capacitor Selection....................................................... 32 Typical Performance Characteristics ........................................... 13 Input Capacitor Selection .......................................................... 33 Theory of Operation ...................................................................... 19 Low-Side Power Device Selection ............................................ 33 Buck Regulator Operational Modes ......................................... 19 Programming the UVLO Input ................................................ 33 Adjustable and Fixed Output Voltages .................................... 19 Compensation Components Design ....................................... 34 Dynamic Voltage Scaling (DVS) .............................................. 20 Power Dissipation....................................................................... 34 Internal Regulators (VREG and VDD) ................................... 20 Junction Temperature ................................................................ 35 Separate Supply Applications .................................................... 20 Design Example .............................................................................. 36 Low-Side Device Selection ........................................................ 20 Setting the Switching Frequency .............................................. 36 Bootstrap Circuitry .................................................................... 20 Setting the Output Voltage ........................................................ 36 Active Output Discharge Switch .............................................. 21 Setting the Current Limit .......................................................... 36 Precision Enabling ...................................................................... 21 Selecting the Inductor ................................................................ 36 Oscillator ..................................................................................... 21 Selecting the Output Capacitor ................................................ 36 Synchronization Input/Output ................................................. 22 Selecting the Low-Side MOSFET ............................................. 37 Soft Start ...................................................................................... 22 Designing the Compensation Network ................................... 37 Parallel Operation....................................................................... 23 Selecting the Soft Start Time..................................................... 37 Startup with Precharged Output .............................................. 23 Selecting the Input Capacitor ................................................... 37 Current-Limit Protection .......................................................... 23 Recommended External Components .................................... 37 Frequency Foldback ................................................................... 24 Circuit Board Layout Recommendations ................................... 39 Hiccup Protection ...................................................................... 24 Typical Application Circuits ......................................................... 40 Latch-Off Protection .................................................................. 24 Register Map ................................................................................... 43 Undervoltage Lockout (UVLO) ............................................... 25 Detailed Register Descriptions ..................................................... 44 Power-Good Function ............................................................... 25 Register 1: PCTRL (Channel Enable Control), Address 0x01 ............................................................................... 44 Interrupt Function ...................................................................... 25 Register 2: VID1 (VID Setting for Channel 1), Thermal Shutdown ..................................................................... 26 Address 0x02 ............................................................................... 44 Overheat Detection .................................................................... 26 Register 3: VID23 (VID Setting for Channel 2 and Channel 3), Low Input Voltage Detection .................................................... 26 Address 0x03 ............................................................................... 45 Rev. B Page 2 of 55

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