Triple Buck Regulator Integrated Power Solution Data Sheet ADP5055 FEATURES TYPICAL APPLICATION CIRCUIT Wide input voltage range: 2.75 V to 18 V ADP5055 Bias input voltage range: 4.5 V to 18 V VBIAS (V = 4.5V RT BIAS INT TO 18V) Operation up to 150C junction temperature VREG OSC V REG C1 SYNC/MODE PMBus-compatible interface with configurable address FB1 voltage accuracy (default): 0.62% to +0.69% (40C RAMP1 2.75V T +125C) J BST1 TO 18V PVIN1 C3 Channel 1 and Channel 2: 7 A synchronous buck regulator L1 C2 VOUT1 SW1 CHANNEL 1 (9.4 A minimum valley current-limit threshold) 7A BUCK FB1 COMP1 C4 Channel 1 and Channel 2: 14 A output in parallel operation PGND EN1 Channel 3: 3 A synchronous buck regulator (4.2 A minimum RAMP2 valley current-limit threshold) BST2 8-bit precision DAC for DVS PVIN2 C6 L2 VOUT2 C5 SW2 Adjustable feedback voltage range: 408 mV to 790.5 mV CHANNEL 2 7A BUCK COMP2 FB2 C7 per 1.5 mV step PGND Upper and lower threshold limit setting EN2 250 kHz to 2500 kHz adjustable switching frequency range RAMP3 BST3 External compensation for fast load transient response PVIN3 C9 L3 Precision enable pin with 0.615 V accurate threshold SW3 VOUT3 C8 CHANNEL 3 3A BUCK FB3 Programmable power-up and power-down sequence COMP3 C10 PGND Selective active output discharge switch EN3 Selective FPWM/PSM mode selection PWRGD Frequency synchronization input or output SCL MISC PMBus CFG1 SDA Power-good flag on selective channels CFG2 UVLO, overcurrent protection, and TSD protection GND 43-terminal, 5.00 mm 5.50 mm LGA package APPLICATIONS Figure 1. Small cell base stations The switching frequency of the ADP5055 can be programmed Field programmable gate array (FPGA) and processor or synchronized to an external clock. The ADP5055 contains an applications enable pin (ENx) on each channel for simple power-up Security and surveillance sequencing or adjustable undervoltage lockout (UVLO) threshold. Medical applications The ADP5055 integrates a high precision 8-bit digital-to-analog GENERAL DESCRIPTION converter (DAC) to enable the output voltage dynamic voltage The ADP5055 combines three high performance buck regulators scaling (DVS) via the PMBus-compatible, 2-wire interface. The in a 43-terminal land grid array (LGA) package that meets the PMBus interface provides other flexible configurations, such as demanding performance and board space requirements. The start-up and shutdown sequence control, individual forced pulse- device enables direct connection to high input voltages up to width modulation or power saving mode (FPWM or PSM) 18 V with no preregulators. selection, an output discharge switch, and a power-good signal. All channels integrate both high-side and low-side power metal- The ADP5055 is rated at 40C to +150C junction temperature. oxide semiconductor field effect transistors (MOSFETs) to achieve Note that throughout this data sheet, multifunction pins, such an efficiency optimized solution. Channel 1 and Channel 2 deliver as SYNC/MODE, are referred to either by the entire pin name a programmable output current of 3.5 A or 7 A or provide a single or by a single function of the pin, for example, SYNC, when output with up to 14 A of current in parallel operation. Channel 3 only that function is relevant. delivers a programmable output current of 1.5 A or 3 A. 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Trademarks and registered trademarks are the property of their respective owners. 1726 9-0 0 1ADP5055 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Power-Up at High Temperature ............................................... 25 Applications ....................................................................................... 1 Thermal Shutdown .................................................................... 25 General Description ......................................................................... 1 PMBus Interface ............................................................................. 26 Typical Application Circuit ............................................................. 1 SDA and SCL Pins ...................................................................... 26 Revision History ............................................................................... 2 PMBus Addresses ....................................................................... 26 Functional Block Diagram .............................................................. 3 PMBus Interface Timing Diagrams ......................................... 27 Specifications ..................................................................................... 4 Applications Information .............................................................. 28 Buck Regulator Specifications .................................................... 5 Programming the Adjustable Output Voltage ........................ 28 PMBus Interface Timing Specifications .................................... 8 Voltage Conversion Limitations ............................................... 28 Absolute Maximum Ratings ............................................................ 9 Current-Limit Setting ................................................................ 28 Thermal Resistance ...................................................................... 9 Soft Start Setting ......................................................................... 28 ESD Caution .................................................................................. 9 Inductor Selection ...................................................................... 28 Pin Configuration and Function Descriptions ........................... 10 Output Capacitor Selection....................................................... 29 Typical Performance Characteristics ........................................... 12 Input Capacitor Selection .......................................................... 30 Theory of Operation ...................................................................... 17 Programming the UVLO Input ................................................ 30 Buck Regulator Operational Modes ......................................... 17 Slope Compensation Setting ..................................................... 30 Adjustable Output Voltages ....................................................... 18 Compensation Components Design ....................................... 30 Dynamic Voltage Scaling (DVS) .............................................. 18 Power Dissipation....................................................................... 31 Internal Regulator (VREG) ....................................................... 18 Junction Temperature ................................................................ 32 Separate Supply Applications .................................................... 18 Typical Application Circuits ..................................................... 33 Bootstrap Circuitry .................................................................... 19 Design Example .............................................................................. 36 Active Output Discharge Switch .............................................. 19 Setting the Switching Frequency .............................................. 36 Precision Enabling ...................................................................... 19 Setting the Output Voltage ........................................................ 36 Sequence Mode ........................................................................... 20 Setting the Configuations (CFG1 and CFG2) ........................ 36 Oscillator ..................................................................................... 20 Selecting the Inductor ................................................................ 36 Synchronization Input and Output .......................................... 21 Selecting the Output Capacitor ................................................ 37 Soft Start ...................................................................................... 21 Designing the Compensation Network ................................... 37 Function Configurations (CFG1 and CFG2) ......................... 21 Selecting the Input Capacitor ................................................... 37 Parallel Operation ...................................................................... 22 PCB Layout Recommendations .................................................... 38 Fast Transient Mode ................................................................... 24 Register Map ................................................................................... 39 Startup with Precharged Output .............................................. 24 Register Details ............................................................................... 40 Current-Limit Protection .......................................................... 24 Outline Dimensions ....................................................................... 50 UVLO ........................................................................................... 25 Ordering Guide .......................................................................... 50 Power-Good Function ............................................................... 25 REVISION HISTORY 1/2022Revision 0: Initial Version Rev. 0 Page 2 of 50