1 A/0.6 A, DC-to-DC Switching Regulator with Independent Positive and Negative Outputs Data Sheet ADP5070 FEATURES TYPICAL APPLICATION CIRCUIT Wide input supply voltage range: 2.85 V to 15 V ADP5070 SS INBK Generates well regulated, independently resistor R C1 L1 programmable V and V outputs POS NEG COMP1 V C POS C1 Boost regulator to generate V output POS SW1 EN1 D1 Adjustable positive output to 39 V C R VREG FT1 FB1 Integrated 1.0 A main switch VREG C OUT1 R FB1 Optional single-ended primary-inductor converter (SEPIC) PVIN1 V IN PVIN2 configuration for automatic step-up/step-down PGND PVINSYS C IN1 C VREF Inverting regulator to generate V output NEG VREF EN2 Adjustable negative output to V 39 V IN R FB2 C OUT2 R C2 Integrated 0.6 A main switch FB2 COMP2 R C FT2 True shutdown for both positive and negative outputs C2 SYNC/FREQ SW2 1.2 MHz/2.4 MHz switching frequency with optional external SLEW V NEG D2 SEQ frequency synchronization from 1.0 MHz to 2.6 MHz AGND L2 Resistor programmable soft start timer Slew rate control for lower system noise Figure 1. Individual precision enable and flexible start-up sequence control for symmetric start, V first, or V first POS NEG Out-of-phase operation UVLO, OCP, OVP, and TSD protection 4 mm 4 mm, 20-lead LFCSP and 20-lead TSSOP 40C to +125C junction temperature range Supported by the ADIsimPower tool set APPLICATIONS Bipolar amplifiers, ADCs, DACs and multiplexers Charge-coupled device (CCD) bias supply Optical module supply RF power amplifier (PA) bias negative supply first. GENERAL DESCRIPTION The ADP5070 includes a fixed internal or resistor programmable The ADP5070 is a dual high performance dc-to-dc regulator that soft start timer to prevent inrush current at power-up. During generates independently regulated positive and negative rails. shutdown, both regulators completely disconnect the loads from The input voltage range of 2.85 V to 15 V supports a wide variety the input supply to provide a true shutdown. of applications. The integrated main switch in both regulators enables generation of an adjustable positive output voltage up to Other key safety features in the ADP5070 include overcurrent +39 V and a negative output voltage down to 39 V below input protection (OCP), overvoltage protection (OVP), thermal voltage. shutdown (TSD), and input undervoltage lockout (UVLO). The ADP5070 is available in a 20-lead LFCSP or in a 20-lead The ADP5070 operates at a pin selected 1.2 MHz/2.4 MHz TSSOP and is rated for a 40C to +125C junction temperature switching frequency. The ADP5070 can synchronize with an range. external oscillator from 1.0 MHz to 2.6 MHz to ease noise filtering in sensitive applications. Both regulators implement Table 1. Family Models programmable slew rate control circuitry for the MOSFET Model Boost Switch (A) Inverter Switch (A) driver stage to reduce electromagnetic interference (EMI). ADP5070 1.0 0.6 ADP5071 2.0 1.2 Flexible start-up sequencing is provided with the options of manual enable, simultaneous mode, positive supply first, and Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. Tel: 781.329.4700 20152020 Analog Devices, Inc. All rights reserved. No license is granted by implication or otherwise under any patent or patent rights of Analog Technical Support www.analog.com Devices. Trademarks and registered trademarks are the property of their respective owners. 12068-001ADP5070 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Soft Start ...................................................................................... 15 Applications ...................................................................................... 1 Slew Rate Control ....................................................................... 15 Typical Application Circuit ............................................................ 1 Current-Limit Protection ............................................................ 15 General Description ......................................................................... 1 Overvoltage Protection.............................................................. 15 Revision History ............................................................................... 2 Thermal Shutdown .................................................................... 15 Specifications .................................................................................... 3 Start-Up Sequence ...................................................................... 15 Absolute Maximum Ratings ........................................................... 5 Applications Information ............................................................. 17 Thermal Resistance ...................................................................... 5 ADIsimPower Design Tool ...................................................... 17 ESD Caution.................................................................................. 5 Component Selection ................................................................ 17 Pin Configurations and Function Descriptions ........................... 6 Loop Compensation .................................................................. 20 Typical Performance Characteristics ............................................. 8 Common Applications .............................................................. 22 Theory of Operation ...................................................................... 14 Super Low Noise With Optional LDOs .................................. 24 PWM Mode ................................................................................. 14 SEPIC Step-Up/Step-Down Operation ................................... 25 PSM Mode ................................................................................... 14 Layout Considerations .............................................................. 26 Undervoltage Lockout (UVLO) ............................................... 14 Outline Dimensions ....................................................................... 27 Oscillator and Synchronization ................................................ 14 Ordering Guide .......................................................................... 27 Internal Regulators ..................................................................... 14 Precision Enabling ..................................................................... 15 REVISION HISTORY 7/2020Rev. D to Rev. E 6/2015Rev. 0 to Rev. A Changes to Figure 48 ..................................................................... 24 Added 20-Lead TSSOP ...................................................... Universal Changes to Table 3 and Table 4 ...................................................... 5 3/2019Rev. C to Rev. D Added Figure 3, Renumbered Sequentially ................................... 6 Changes to Figure 48 ..................................................................... 24 Changes to Figure 29 Caption and Figure 32 Caption ............. 11 Changes to Figure 37 Caption to Figure 39 Caption ................ 13 6/2018Rev. B to Rev. C Changes to Internal Regulators Section ...................................... 14 Changes to Figure 34, Figure 35, and Figure 36 ......................... 13 Change to Soft Start Section ......................................................... 15 Changes to Output Capacitors Section, Soft Start Resistor Section, 7/2017Rev. A to Rev. B and Diodes Section ......................................................................... 18 Changes to Table 10 and Table 11 ............................................... 23 Changes to Figure 50 Caption ...................................................... 26 Updated Outline Dimensions ....................................................... 27 Added Figure 51 ............................................................................. 26 Changes to Ordering Guide .......................................................... 27 Updated Outline Dimensions ...................................................... 27 Changes to Ordering Guide .......................................................... 27 2/2015Revision 0: Initial Version Rev. E Page 2 of 27