1 A/0.6 A DC to DC Switching Regulator with Independent Positive and Negative Outputs Data Sheet ADP5072 FEATURES TYPICAL APPLICATION CIRCUIT V IN Input supply voltage range: 2.85 V to 5.5 V ADP5072 Generates well regulated, independently resistor L1 SS V programmable V and V outputs POS NEG R POS C1 SW1 COMP1 Boost regulator to generate V output POS D1 C SW1 C1 R FT1 Adjustable positive output to 35 V EN1 FB1 R Integrated 1.0 A main switch FB1 C OUT1 PVIN Inverting regulator to generate V output NEG V PVIN IN PGND AVIN Adjustable negative output to 30 V C IN C PGND VREF Integrated 0.6 A main switch VREF EN2 1.2 MHz/2.4 MHz switching frequency with optional external C R FB2 OUT2 R C2 frequency synchronization from 1.0 MHz to 2.6 MHz FB2 COMP2 R FT2 C Resistor programmable soft start timer C2 SYNC SW2 Slew rate control for lower system noise SLEW V NEG D2 SEQ Individual precision enable and flexible start-up sequence AGND L2 control for symmetric start, V first, or V first POS NEG Out of phase operation Figure 1. UVLO, OCP, OVP, and TSD protection 1.61 mm 2.18 mm, 20-ball WLCSP 40C to +125C junction temperature range APPLICATIONS Bipolar amplifiers, ADCs, DACs, and multiplexers Charge coupled device (CCD) bias supply Optical module supply RF power amplifier bias Time of flight module supply Other key safety features in the ADP5072 include overcurrent GENERAL DESCRIPTION protection (OCP), overvoltage protection (OVP), thermal The ADP5072 is a dual, high performance dc-to-dc regulator that shutdown (TSD), and input undervoltage lockout (UVLO). generates independently regulated positive and negative rails. The ADP5072 is available in a 20-ball WLCSP and is rated for a The input voltage range of 2.85 V to 5.5 V supports a wide 40C to +125C junction temperature range. variety of applications. The integrated main switch in both regulators enables generation of an adjustable positive output Table 1. Family Models voltage up to 35 V and a negative output voltage down to Boost Inverter Model Switch (A) Switch (A) Package 30 V. ADP5070 1.0 0.6 20-lead LFCSP (4 mm 4 mm) and The ADP5072 operates at a pin selected 1.2 MHz or 2.4 MHz 20-lead TSSOP switching frequency. The ADP5072 can synchronize with an ADP5071 2.0 1.2 20-lead LFCSP (4 mm 4 mm) and 20-lead TSSOP external oscillator from 1.0 MHz to 2.6 MHz to ease noise filtering ADP5072 1.0 0.6 20-ball WLCSP (1.61 mm 2.18 mm) in sensitive applications. Both regulators implement programma- ADP5073 Not 1.2 16-lead LFCSP (3 mm 3 mm) ble slew rate control circuitry for the MOSFET driver stage to applicable reduce electromagnetic interference (EMI). Flexible start-up ADP5074 Not 2.4 16-lead LFCSP (3 mm 3 mm) sequencing is provided with the options of manual enable, applicable ADP5075 Not 0.8 12-ball WLCSP (1.61 mm 2.18 mm) simultaneous mode, positive supply first, and negative supply first. applicable The ADP5072 includes a fixed internal or resistor programmable ADP5076 2.0 1.2 20-ball WLCSP (1.61 mm 2.18 mm) soft start timer to prevent inrush current at power-up. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. Tel: 781.329.4700 20192020 Analog Devices, Inc. All rights reserved. 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Trademarks and registered trademarks are the property of their respective owners. 12069-001ADP5072 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Precision Enabling ..................................................................... 14 Applications ...................................................................................... 1 Soft Start ...................................................................................... 14 Typical Application Circuit ............................................................ 1 Slew Rate Control ....................................................................... 14 General Description ......................................................................... 1 Current-Limit Protection ............................................................ 14 Revision History ............................................................................... 2 Overvoltage Protection.............................................................. 14 Specifications .................................................................................... 3 Thermal Shutdown .................................................................... 14 Absolute Maximum Ratings ........................................................... 5 Start-Up Sequence ...................................................................... 14 Thermal Resistance ...................................................................... 5 Applications Information ............................................................. 16 ESD Caution.................................................................................. 5 Component Selection ................................................................ 16 Pin Configuration and Function Descriptions ............................ 6 Output Capacitors ...................................................................... 17 Typical Performance Characteristics ............................................. 7 Loop Compensation .................................................................. 19 Theory of Operation ...................................................................... 13 Common Applications .............................................................. 20 Pulse Width Modulation (PWM) Mode ................................. 13 Layout Considerations .............................................................. 22 Pulse Skip Modulation Mode ................................................... 13 Outline Dimensions ....................................................................... 23 Undervoltage Lockout (UVLO) ............................................... 13 Ordering Guide .......................................................................... 23 Oscillator and Synchronization ................................................ 13 Internal Regulator ...................................................................... 13 REVISION HISTORY 11/2020Rev. 0 to Rev. A Added Table 9 Renumbered Sequentially ................................. 16 Changes to Applications Section and Table 1 .............................. 1 Changes to Output Capacitors Section, Diodes Section, and Changes to Table 2 ........................................................................... 3 Inductor Selection for the Boost Regulator Section .................. 17 Changes to Thermal Resistance Section........................................ 5 Changes to Boost Regulator Section and Inverting Changes to Table 5 ........................................................................... 6 Regulator Section ........................................................................... 19 Changes to Figure 33 Caption, Figure 36, Figure 37, and Changes to Common Applications Section and Figure 46 ...... 20 Figure 38 .......................................................................................... 12 Added Table 10 ............................................................................... 20 Changes to Slew Rate Control Section, Start-Up Sequence Changes to Table 11 and Table 12 ............................................... 21 Section, and Table 7 ....................................................................... 14 Changes to Layout Considerations Section ................................ 22 Changes to Table 8 ......................................................................... 16 1/2019Revision 0: Initial Version Rev. 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