2.4 A, DC-to-DC Inverting Regulator Data Sheet ADP5074 FEATURES TYPICAL APPLICATION CIRCUIT Wide input voltage range: 2.85 V to 15 V C VREF Adjustable negative output to V 39 V AVIN VREF IN Integrated 2.4 A main switch V IN PVIN R FB C IN 1.2 MHz/2.4 MHz switching frequency with optional external ADP5074 FB frequency synchronization from 1.0 MHz to 2.6 MHz R FT ON Resistor programmable soft start timer D1 EN OFF V SW OUT Slew rate control for lower system noise C VREG C OUT VREG Precision enable control L1 Power-good output SS UVLO, OCP, OVP, and TSD protection PWRGD PWRGD SLEW 3 mm 3 mm, 16-lead LFCSP 40C to +125C junction temperature SYNC/FREQ COMP R C C Supported by the ADIsimPower tool set C GND APPLICATIONS Figure 1. Bipolar amplifiers, ADCs, digital-to-analog converters (DACs), and multiplexers High speed converters Radio frequency (RF) power amplifier (PA) bias Optical modules GENERAL DESCRIPTION The ADP5074 is a high performance dc-to-dc inverting regulator Other key safety features in the ADP5074 include overcurrent used to generate negative supply rails. protection (OCP), overvoltage protection (OVP), thermal shutdown (TSD), and input undervoltage lockout (UVLO). The input voltage range of 2.85 V to 15 V supports a wide variety of applications. The integrated main switch enables the generation of The ADP5074 is available in a 16-lead LFCSP and is rated for a an adjustable negative output voltage down to 39 V below the 40C to +125C operating junction temperature range. input voltage. Table 1. Related Devices The ADP5074 operates at a pin selected 1.2 MHz/2.4 MHz Boost Inverter switching frequency. The ADP5074 can synchronize with an Device Switch (A) Switch (A) Package external oscillator from 1.0 MHz to 2.6 MHz to ease noise ADP5070 1.0 0.6 20-lead LFCSP (4 mm filtering in sensitive applications. The regulator implements 4 mm) and TSSOP programmable slew rate control circuitry for the MOSFET ADP5071 2.0 1.2 20-lead LFCSP (4 mm driver stage to reduce electromagnetic interference (EMI). 4 mm) and TSSOP ADP5073 Not 1.2 16-lead LFCSP (3 mm The ADP5074 includes a fixed internal or resistor programmable applicable 3 mm) soft start timer to prevent inrush current at power-up. During ADP5074 Not 2.4 16-lead LFCSP (3 mm shutdown, the regulator completely disconnects the load from the applicable 3 mm) input supply to provide a true shutdown. A power good pin is ADP5075 Not 0.8 12-ball WLCSP available to indicate the output is stable. applicable (1.61 mm 2.18 mm) Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20152017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 12818-001ADP5074 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Internal Regulators ..................................................................... 10 Applications ....................................................................................... 1 Precision Enabling...................................................................... 11 Typical Application Circuit ............................................................. 1 Soft Start ...................................................................................... 11 General Description ......................................................................... 1 Slew Rate Control ....................................................................... 11 Revision History ............................................................................... 2 Current-Limit Protection ............................................................ 11 Specifications ..................................................................................... 3 Overvoltage Protection .............................................................. 11 Absolute Maximum Ratings ............................................................ 5 Power Good ................................................................................ 11 Thermal Resistance ...................................................................... 5 Applications Information .............................................................. 12 ESD Caution .................................................................................. 5 ADIsimPower Design Tool ....................................................... 12 Pin Configuration and Function Descriptions ............................. 6 Component Selection ................................................................ 12 Typical Performance Characteristics ............................................. 7 Common Applications .............................................................. 15 Theory of Operation ...................................................................... 10 Layout Considerations ............................................................... 16 PWM Mode ................................................................................. 10 Outline Dimensions ....................................................................... 17 Skip Mode .................................................................................... 10 Ordering Guide .......................................................................... 17 Undervoltage Lockout (UVLO) ............................................... 10 Oscillator and Synchronization ................................................ 10 REVISION HISTORY 10/2017Rev. 0 to Rev. A Updated Outline Dimensions ....................................................... 17 Changes to Ordering Guide .......................................................... 17 10/2015Revision 0: Initial Version Rev. A Page 2 of 17